radv: Support SDMA in radv_cs_write_data_head.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25833>
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@@ -228,15 +228,25 @@ ALWAYS_INLINE static unsigned
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radv_cs_write_data_head(const struct radv_device *device, struct radeon_cmdbuf *cs, const enum radv_queue_family qf,
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const unsigned engine_sel, const uint64_t va, const unsigned count, const bool predicating)
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{
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assert(qf == RADV_QUEUE_GENERAL || qf == RADV_QUEUE_COMPUTE);
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/* Return the correct cdw at the end of the packet so the caller can assert it. */
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const unsigned cdw_end = radeon_check_space(device->ws, cs, 4 + count);
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, predicating));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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if (qf == RADV_QUEUE_GENERAL || qf == RADV_QUEUE_COMPUTE) {
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, predicating));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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} else if (qf == RADV_QUEUE_TRANSFER) {
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/* Vulkan transfer queues don't support conditional rendering, so we can ignore predication here.
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* Furthermore, we can ignore the engine selection here, it is meaningless to the SDMA.
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*/
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, count - 1);
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} else {
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unreachable("unsupported queue family");
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}
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return cdw_end;
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}
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