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radv: rework passing draw info via radv_draw_info

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More like BDA style. For future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33404>
This commit is contained in:
Samuel Pitoiset
2025-01-02 16:03:22 +01:00
parent 6f34be88d9
commit 03cacc1406
1 changed files with 87 additions and 118 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+87 -118
View File
@@ -6185,23 +6185,20 @@ struct radv_draw_info {
bool indexed;
/**
* Indirect draw parameters resource.
* Indirect draw parameters.
*/
struct radv_buffer *indirect;
uint64_t indirect_offset;
uint64_t indirect_va;
uint32_t stride;
/**
* Draw count parameters resource.
* Draw count parameters VA.
*/
struct radv_buffer *count_buffer;
uint64_t count_buffer_offset;
uint64_t count_va;
/**
* Stream output parameters resource.
* Stream output parameters VA.
*/
struct radv_buffer *strmout_buffer;
uint64_t strmout_buffer_offset;
uint64_t strmout_va;
};
struct radv_prim_vertex_count {
@@ -6454,8 +6451,8 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
if (gpu_info->gfx_level >= GFX10) {
gfx10_emit_ge_cntl(cmd_buffer);
} else {
radv_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, draw_info->indirect,
!!draw_info->strmout_buffer, draw_info->indirect ? 0 : draw_info->count);
radv_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, !!draw_info->indirect_va,
!!draw_info->strmout_va, draw_info->indirect_va ? 0 : draw_info->count);
}
/* RDNA2 is affected by a hardware bug when instance packing is enabled for adjacent primitive
@@ -6463,7 +6460,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
* be applied for indexed and non-indexed draws.
*/
if (gpu_info->gfx_level == GFX10_3 && state->active_pipeline_queries > 0 &&
(draw_info->instance_count > 1 || draw_info->indirect) &&
(draw_info->instance_count > 1 || draw_info->indirect_va) &&
(topology == V_008958_DI_PT_LINELIST_ADJ || topology == V_008958_DI_PT_LINESTRIP_ADJ ||
topology == V_008958_DI_PT_TRILIST_ADJ || topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
disable_instance_packing = true;
@@ -9989,24 +9986,12 @@ ALWAYS_INLINE static void
radv_emit_indirect_mesh_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info)
{
const struct radv_cmd_state *state = &cmd_buffer->state;
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radeon_winsys *ws = device->ws;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const uint64_t va = radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
const uint64_t count_va = !info->count_buffer ? 0
: radv_buffer_get_va(info->count_buffer->bo) +
info->count_buffer->offset + info->count_buffer_offset;
radv_cs_add_buffer(ws, cs, info->indirect->bo);
if (info->count_buffer) {
radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
}
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
radeon_emit(cs, 1);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, info->indirect_va);
radeon_emit(cs, info->indirect_va >> 32);
if (state->uses_drawid) {
const struct radv_shader *mesh_shader = state->shaders[MESA_SHADER_MESH];
@@ -10016,11 +10001,11 @@ radv_emit_indirect_mesh_draw_packets(struct radv_cmd_buffer *cmd_buffer, const s
}
if (!state->render.view_mask) {
radv_cs_emit_indirect_mesh_draw_packet(cmd_buffer, info->count, count_va, info->stride);
radv_cs_emit_indirect_mesh_draw_packet(cmd_buffer, info->count, info->count_va, info->stride);
} else {
u_foreach_bit (i, state->render.view_mask) {
radv_emit_view_index(&cmd_buffer->state, cs, i);
radv_cs_emit_indirect_mesh_draw_packet(cmd_buffer, info->count, count_va, info->stride);
radv_cs_emit_indirect_mesh_draw_packet(cmd_buffer, info->count, info->count_va, info->stride);
}
}
}
@@ -10058,19 +10043,10 @@ radv_emit_indirect_taskmesh_draw_packets(const struct radv_device *device, struc
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint32_t view_mask = cmd_state->render.view_mask;
struct radeon_winsys *ws = device->ws;
const unsigned num_views = MAX2(1, util_bitcount(view_mask));
unsigned ace_predication_size = num_views * 11; /* DISPATCH_TASKMESH_INDIRECT_MULTI_ACE size */
const uint64_t va = radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
const uint64_t count_va = !info->count_buffer ? 0
: radv_buffer_get_va(info->count_buffer->bo) +
info->count_buffer->offset + info->count_buffer_offset;
if (count_va)
radv_cs_add_buffer(ws, ace_cs, info->count_buffer->bo);
if (pdev->info.has_taskmesh_indirect0_bug && count_va) {
if (pdev->info.has_taskmesh_indirect0_bug && info->count_va) {
/* MEC firmware bug workaround.
* When the count buffer contains zero, DISPATCH_TASKMESH_INDIRECT_MULTI_ACE hangs.
* - We must ensure that DISPATCH_TASKMESH_INDIRECT_MULTI_ACE
@@ -10095,12 +10071,11 @@ radv_emit_indirect_taskmesh_draw_packets(const struct radv_device *device, struc
ace_predication_size += 2 * 5 + 6 + 6 * num_views;
}
radv_cs_add_buffer(ws, ace_cs, info->indirect->bo);
radv_cs_emit_compute_predication(device, cmd_state, ace_cs, cmd_state->mec_inv_pred_va,
&cmd_state->mec_inv_pred_emitted, ace_predication_size);
if (workaround_cond_va) {
radv_emit_cond_exec(device, ace_cs, count_va,
radv_emit_cond_exec(device, ace_cs, info->count_va,
6 + 11 * num_views /* 1x COPY_DATA + Nx DISPATCH_TASKMESH_INDIRECT_MULTI_ACE */);
radeon_emit(ace_cs, PKT3(PKT3_COPY_DATA, 4, 0));
@@ -10113,15 +10088,15 @@ radv_emit_indirect_taskmesh_draw_packets(const struct radv_device *device, struc
}
if (!view_mask) {
radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(device, cmd_state, ace_cs, va, info->count, count_va,
info->stride);
radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(device, cmd_state, ace_cs, info->indirect_va,
info->count, info->count_va, info->stride);
radv_cs_emit_dispatch_taskmesh_gfx_packet(device, cmd_state, cs);
} else {
u_foreach_bit (view, view_mask) {
radv_emit_view_index(cmd_state, cs, view);
radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(device, cmd_state, ace_cs, va, info->count, count_va,
info->stride);
radv_cs_emit_dispatch_taskmesh_indirect_multi_ace_packet(device, cmd_state, ace_cs, info->indirect_va,
info->count, info->count_va, info->stride);
radv_cs_emit_dispatch_taskmesh_gfx_packet(device, cmd_state, cs);
}
}
@@ -10139,32 +10114,20 @@ static void
radv_emit_indirect_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info)
{
const struct radv_cmd_state *state = &cmd_buffer->state;
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radeon_winsys *ws = device->ws;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const uint64_t va = radv_buffer_get_va(info->indirect->bo) + info->indirect->offset + info->indirect_offset;
const uint64_t count_va = info->count_buffer ? radv_buffer_get_va(info->count_buffer->bo) +
info->count_buffer->offset + info->count_buffer_offset
: 0;
radv_cs_add_buffer(ws, cs, info->indirect->bo);
radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
radeon_emit(cs, 1);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
if (info->count_buffer) {
radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
}
radeon_emit(cs, info->indirect_va);
radeon_emit(cs, info->indirect_va >> 32);
if (!state->render.view_mask) {
radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va, info->stride);
radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, info->count_va, info->stride);
} else {
u_foreach_bit (i, state->render.view_mask) {
radv_emit_view_index(&cmd_buffer->state, cs, i);
radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va, info->stride);
radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, info->count_va, info->stride);
}
}
}
@@ -10213,7 +10176,7 @@ radv_get_needed_dynamic_states(struct radv_cmd_buffer *cmd_buffer)
static bool
radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info)
{
if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_va)
return true;
uint64_t used_dynamic_states = radv_get_needed_dynamic_states(cmd_buffer);
@@ -10909,7 +10872,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
RADV_DYNAMIC_ALPHA_TO_ONE_ENABLE)))
radv_emit_db_shader_control(cmd_buffer);
if (info->indexed && info->indirect && cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
if (info->indexed && info->indirect_va && cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
radv_emit_index_buffer(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_ENABLE)
@@ -11074,7 +11037,7 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info
ASSERTED const unsigned cdw_max = radeon_check_space(device->ws, cmd_buffer->cs, 4096 + 128 * (drawCount - 1));
if (likely(!info->indirect)) {
if (likely(!info->indirect_va)) {
/* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
* no workaround for indirect draws, but we can at least skip
* direct draws.
@@ -11083,7 +11046,7 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info
return false;
/* Handle count == 0. */
if (unlikely(!info->count && !info->strmout_buffer))
if (unlikely(!info->count && !info->strmout_va))
return false;
}
@@ -11141,7 +11104,7 @@ radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info
if (!dgc)
radv_describe_draw(cmd_buffer);
if (likely(!info->indirect)) {
if (likely(!info->indirect_va)) {
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
assert(state->vtx_base_sgpr);
@@ -11204,7 +11167,7 @@ radv_before_taskmesh_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (!dgc)
radv_describe_draw(cmd_buffer);
if (likely(!info->indirect)) {
if (likely(!info->indirect_va)) {
struct radv_cmd_state *state = &cmd_buffer->state;
if (unlikely(state->last_num_instances != 1)) {
struct radeon_cmdbuf *cs = cmd_buffer->cs;
@@ -11258,8 +11221,8 @@ radv_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t insta
info.count = vertexCount;
info.instance_count = instanceCount;
info.first_instance = firstInstance;
info.strmout_buffer = NULL;
info.indirect = NULL;
info.strmout_va = 0;
info.indirect_va = 0;
info.indexed = false;
if (!radv_before_draw(cmd_buffer, &info, 1, false))
@@ -11282,8 +11245,8 @@ radv_CmdDrawMultiEXT(VkCommandBuffer commandBuffer, uint32_t drawCount, const Vk
info.count = pVertexInfo->vertexCount;
info.instance_count = instanceCount;
info.first_instance = firstInstance;
info.strmout_buffer = NULL;
info.indirect = NULL;
info.strmout_va = 0;
info.indirect_va = 0;
info.indexed = false;
if (!radv_before_draw(cmd_buffer, &info, drawCount, false))
@@ -11303,8 +11266,8 @@ radv_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t
info.count = indexCount;
info.instance_count = instanceCount;
info.first_instance = firstInstance;
info.strmout_buffer = NULL;
info.indirect = NULL;
info.strmout_va = 0;
info.indirect_va = 0;
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
@@ -11329,8 +11292,8 @@ radv_CmdDrawMultiIndexedEXT(VkCommandBuffer commandBuffer, uint32_t drawCount,
info.count = minfo->indexCount;
info.instance_count = instanceCount;
info.first_instance = firstInstance;
info.strmout_buffer = NULL;
info.indirect = NULL;
info.strmout_va = 0;
info.indirect_va = 0;
if (!radv_before_draw(cmd_buffer, &info, drawCount, false))
return;
@@ -11344,17 +11307,19 @@ radv_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDeviceSi
{
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
VK_FROM_HANDLE(radv_buffer, buffer, _buffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_draw_info info;
info.count = drawCount;
info.indirect = buffer;
info.indirect_offset = offset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.stride = stride;
info.strmout_buffer = NULL;
info.count_buffer = NULL;
info.strmout_va = 0;
info.count_va = 0;
info.indexed = false;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
radv_emit_indirect_draw_packets(cmd_buffer, &info);
@@ -11367,17 +11332,19 @@ radv_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkD
{
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
VK_FROM_HANDLE(radv_buffer, buffer, _buffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_draw_info info;
info.indexed = true;
info.count = drawCount;
info.indirect = buffer;
info.indirect_offset = offset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.stride = stride;
info.count_buffer = NULL;
info.strmout_buffer = NULL;
info.count_va = 0;
info.strmout_va = 0;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
radv_emit_indirect_draw_packets(cmd_buffer, &info);
@@ -11391,18 +11358,20 @@ radv_CmdDrawIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDev
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
VK_FROM_HANDLE(radv_buffer, buffer, _buffer);
VK_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_draw_info info;
info.count = maxDrawCount;
info.indirect = buffer;
info.indirect_offset = offset;
info.count_buffer = count_buffer;
info.count_buffer_offset = countBufferOffset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.count_va = radv_buffer_get_va(count_buffer->bo) + count_buffer->offset + countBufferOffset;
info.stride = stride;
info.strmout_buffer = NULL;
info.strmout_va = 0;
info.indexed = false;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
radv_cs_add_buffer(device->ws, cmd_buffer->cs, count_buffer->bo);
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
radv_emit_indirect_draw_packets(cmd_buffer, &info);
@@ -11417,18 +11386,20 @@ radv_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
VK_FROM_HANDLE(radv_buffer, buffer, _buffer);
VK_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_draw_info info;
info.indexed = true;
info.count = maxDrawCount;
info.indirect = buffer;
info.indirect_offset = offset;
info.count_buffer = count_buffer;
info.count_buffer_offset = countBufferOffset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.count_va = radv_buffer_get_va(count_buffer->bo) + count_buffer->offset + countBufferOffset;
info.stride = stride;
info.strmout_buffer = NULL;
info.strmout_va = 0;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
radv_cs_add_buffer(device->ws, cmd_buffer->cs, count_buffer->bo);
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
radv_emit_indirect_draw_packets(cmd_buffer, &info);
@@ -11447,9 +11418,9 @@ radv_CmdDrawMeshTasksEXT(VkCommandBuffer commandBuffer, uint32_t x, uint32_t y,
info.first_instance = 0;
info.stride = 0;
info.indexed = false;
info.strmout_buffer = NULL;
info.count_buffer = NULL;
info.indirect = NULL;
info.strmout_va = 0;
info.count_va = 0;
info.indirect_va = 0;
if (!radv_before_taskmesh_draw(cmd_buffer, &info, 1, false))
return;
@@ -11472,15 +11443,16 @@ radv_CmdDrawMeshTasksIndirectEXT(VkCommandBuffer commandBuffer, VkBuffer _buffer
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
struct radv_draw_info info;
info.indirect = buffer;
info.indirect_offset = offset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.stride = stride;
info.count = drawCount;
info.strmout_buffer = NULL;
info.count_buffer = NULL;
info.strmout_va = 0;
info.count_va = 0;
info.indexed = false;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
if (!radv_before_taskmesh_draw(cmd_buffer, &info, drawCount, false))
return;
@@ -11507,23 +11479,24 @@ radv_CmdDrawMeshTasksIndirectCountEXT(VkCommandBuffer commandBuffer, VkBuffer _b
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_draw_info info;
info.indirect = buffer;
info.indirect_offset = offset;
info.indirect_va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
info.stride = stride;
info.count = maxDrawCount;
info.strmout_buffer = NULL;
info.count_buffer = count_buffer;
info.count_buffer_offset = countBufferOffset;
info.strmout_va = 0;
info.count_va = radv_buffer_get_va(count_buffer->bo) + count_buffer->offset + countBufferOffset;
info.indexed = false;
info.instance_count = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
radv_cs_add_buffer(device->ws, cmd_buffer->cs, count_buffer->bo);
if (!radv_before_taskmesh_draw(cmd_buffer, &info, maxDrawCount, false))
return;
if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) {
uint64_t workaround_cond_va = 0;
if (pdev->info.has_taskmesh_indirect0_bug && info.count_buffer) {
if (pdev->info.has_taskmesh_indirect0_bug && info.count_va) {
/* Allocate a 32-bit value for the MEC firmware bug workaround. */
uint32_t workaround_cond_init = 0;
uint32_t workaround_cond_off;
@@ -11648,7 +11621,7 @@ radv_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, VkBool32 isPr
} else {
struct radv_draw_info info = {
.count = pGeneratedCommandsInfo->maxSequenceCount,
.indirect = (void *)&info,
.indirect_va = (uintptr_t)&info,
.indexed = !!(layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_INDEXED)),
};
@@ -13619,11 +13592,8 @@ radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
va += draw_info->strmout_buffer->offset + draw_info->strmout_buffer_offset;
radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, draw_info->stride);
if (gfx_level >= GFX10) {
@@ -13634,22 +13604,20 @@ radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
radeon_emit(cs, 0);
radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, draw_info->strmout_va);
radeon_emit(cs, draw_info->strmout_va >> 32);
radeon_emit(cs, (R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE - SI_CONTEXT_REG_OFFSET) >> 2);
radeon_emit(cs, 1); /* 1 DWORD */
} else {
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG) | COPY_DATA_WR_CONFIRM);
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, draw_info->strmout_va);
radeon_emit(cs, draw_info->strmout_va >> 32);
radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
radeon_emit(cs, 0); /* unused */
}
radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, counter_offset);
radv_cs_add_buffer(device->ws, cs, draw_info->strmout_buffer->bo);
}
VKAPI_ATTR void VKAPI_CALL
@@ -13666,11 +13634,12 @@ radv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanc
info.count = 0;
info.instance_count = instanceCount;
info.first_instance = firstInstance;
info.strmout_buffer = counterBuffer;
info.strmout_buffer_offset = counterBufferOffset;
info.strmout_va = radv_buffer_get_va(counterBuffer->bo) + counterBuffer->offset + counterBufferOffset;
info.stride = vertexStride;
info.indexed = false;
info.indirect = NULL;
info.indirect_va = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, counterBuffer->bo);
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;