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i965: Fix VS URB entry sizing.

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I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1.

Fixes:
glsl-kwin-blur
glsl-max-varying
glsl-routing
This commit is contained in:
Eric Anholt
2010-10-26 14:36:18 -07:00
parent 88087ba1bf
commit 00bfdac5b8
1 changed files with 1 additions and 1 deletions
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src/mesa/drivers/dri/i965/gen6_urb.c
+1 -1
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@@ -40,7 +40,7 @@ prepare_urb( struct brw_context *brw )
else
brw->urb.nr_gs_entries = 0;
/* CACHE_NEW_VS_PROG */
brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1);
brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
/* Check that the number of URB rows (8 floats each) allocated is less
* than the URB space.