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radv: do not emit the VRS surface VA when it's not enabled

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This shouldn't be necessary because VRS_SURFACE_ENABLE is the toggle
bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
This commit is contained in:
Samuel Pitoiset
2025-04-03 10:26:13 +02:00
committed by Marge Bot
parent 9b11caee40
commit 00354f0a74
1 changed files with 8 additions and 8 deletions
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src/amd/vulkan/radv_cmd_buffer.c
+8 -8
View File
@@ -4848,13 +4848,13 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radeon_begin(cmd_buffer->cs);
if (pdev->info.gfx_level >= GFX11) {
bool vrs_surface_enable = render->vrs_att.iview != NULL;
unsigned xmax = 0, ymax = 0;
uint64_t va = 0;
const bool vrs_surface_enable = render->vrs_att.iview != NULL;
if (vrs_surface_enable) {
const struct radv_image_view *vrs_iview = render->vrs_att.iview;
struct radv_image *vrs_image = vrs_iview->image;
unsigned xmax = 0, ymax = 0;
uint64_t va = 0;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, vrs_image->bindings[0].bo);
@@ -4864,17 +4864,17 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
xmax = vrs_iview->vk.extent.width - 1;
ymax = vrs_iview->vk.extent.height - 1;
radeon_set_context_reg_seq(R_0283F0_PA_SC_VRS_RATE_BASE, 3);
radeon_emit(va >> 8);
radeon_emit(S_0283F4_BASE_256B(va >> 40));
radeon_emit(S_0283F8_X_MAX(xmax) | S_0283F8_Y_MAX(ymax));
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(R_0283E0_PA_SC_VRS_INFO,
S_0283E0_RATE_SW_MODE(vrs_image->planes[0].surface.u.gfx9.swizzle_mode));
}
}
radeon_set_context_reg_seq(R_0283F0_PA_SC_VRS_RATE_BASE, 3);
radeon_emit(va >> 8);
radeon_emit(S_0283F4_BASE_256B(va >> 40));
radeon_emit(S_0283F8_X_MAX(xmax) | S_0283F8_Y_MAX(ymax));
radeon_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, S_0283D0_VRS_SURFACE_ENABLE(vrs_surface_enable));
}