Lionel Landwerlin c871a62a75 brw: move URB channel mask shifting to the lowering pass ...

For example Xe2 uses the LSC and doesn´t need the shifting, so let's
just apply it where it's needed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36757>

2025-08-13 12:01:49 +00:00

..

blorp

all: rename gl_shader_stage to mesa_shader_stage

2025-08-06 10:28:40 +08:00

ci

intel/ci: Fix acer-chromebox-cxi4-puff concurrency

2025-08-05 15:07:40 +00:00

common

all: rename gl_shader_stage to mesa_shader_stage

2025-08-06 10:28:40 +08:00

compiler

brw: move URB channel mask shifting to the lowering pass

2025-08-13 12:01:49 +00:00

decoder

intel/genxml: Remove support for start/end atttributes

2025-07-23 16:02:14 +00:00

dev

all: rename gl_shader_stage to mesa_shader_stage

2025-08-06 10:28:40 +08:00

ds

perfetto: unify init

2025-08-12 13:17:43 +00:00

executor

build: avoid redefining unreachable() which is standard in C23

2025-07-31 17:49:42 +00:00

genxml

anv: actually use the COMPUTE_WALKER_BODY prepacked field

2025-08-11 11:14:52 +00:00

isl

intel: Disable 16x MSAA support on Xe3

2025-08-07 07:30:35 +00:00

nullhw-layer

build: avoid redefining unreachable() which is standard in C23

2025-07-31 17:49:42 +00:00

perf

intel: fork exec_node/list -> brw_exec_node/list as a private Intel utility

2025-07-31 20:23:02 +00:00

shaders

intel: use common CL args

2025-03-06 00:43:59 +00:00

tools

build: avoid redefining unreachable() which is standard in C23

2025-07-31 17:49:42 +00:00

vulkan

anv: stop using descriptor layouts for descriptor buffers push sizes

2025-08-13 12:01:49 +00:00

vulkan_hasvk

all: rename gl_shader_stage_name to mesa_shader_stage_name

2025-08-06 10:28:41 +08:00

meson.build

intel: Add meson option -Dintel-elk

2025-01-30 00:45:59 +00:00