Samuel Pitoiset dfc125d423 radv: fix VRS subpass attachment when HTILE can't be enabled on GFX10.3 ...

On GFX10.3, VRS rates need to be copied to the HTILE buffer but in some
situations, like for mips, it's not always possible to enable HTILE.
In this case, we can fallback to our internal HTILE buffer and tweak
the depth/stencil registers to use this HTILE buffer.

This fixes a bunch of VRS crashes on GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26025>

2023-11-14 09:02:46 +00:00

..

addrlib

amd/common: update addrlib for gfx11.5

2023-10-20 07:32:34 +00:00

ci

radv: fix VRS subpass attachment when HTILE can't be enabled on GFX10.3

2023-11-14 09:02:46 +00:00

common

radv/radeonsi: Forward correct GPU instance to umr.

2023-11-13 13:37:27 +00:00

compiler

aco: skip LS VGPR initialization bug workaround if the prolog exists

2023-11-13 12:09:55 +00:00

drm-shim

amd: rename GFX110x to NAVI31-33

2023-09-30 23:08:47 +00:00

llvm

ac/gpu_info,llvm: trivial cosmetic changes

2023-11-07 19:27:43 +00:00

registers

ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS

2023-10-30 08:10:22 +00:00

vulkan

radv: fix VRS subpass attachment when HTILE can't be enabled on GFX10.3

2023-11-14 09:02:46 +00:00

meson.build

meson: build radeonsi with aco

2023-05-15 02:01:10 +00:00