José Roberto de Souza bb31287d24 intel: Initialize upper 32bits of drm_xe_sync.handle ...

Some compiles don't initialize the upper 32bits of the union that has
u64 addr and u32 handle.
Similar to previous patches but doing that for code in intel/misc.

Cc: stable
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33172>

2025-02-02 21:34:45 -08:00

..

blorp

intel: Add meson option -Dintel-elk

2025-01-30 00:45:59 +00:00

ci

Uprev Piglit to fc8179d319046f45346bcbcc5aaeabebdf151f03

2025-01-31 20:36:33 +00:00

common

intel: Initialize upper 32bits of drm_xe_sync.handle

2025-02-02 21:34:45 -08:00

compiler

intel_clc: remove NIR output support

2025-02-01 07:54:37 +00:00

decoder

intel: Add meson option -Dintel-elk

2025-01-30 00:45:59 +00:00

dev

intel/brw: Use SHADER_OPCODE_SEND_GATHER in Xe3

2025-01-30 04:43:58 +00:00

ds

intel : Expose Shader hashes for utrace and Perfetto

2025-01-10 17:38:16 +00:00

executor

intel: Initialize upper 32bits of drm_xe_sync.handle

2025-02-02 21:34:45 -08:00

genxml

anv/xe3+: Set RegistersPerThread for bindless shader dispatch.

2025-01-29 23:39:32 +00:00

isl

isl: use workaround framework for Wa_1207137018

2025-01-29 12:10:13 +00:00

nullhw-layer

build: pass licensing information in SPDX form

2024-06-29 12:42:49 -07:00

perf

intel/perf: add new perf consts to support more metrics

2025-01-16 00:01:56 +00:00

shaders

intel: move internal shader compile to vtn_bindgen2

2025-02-01 07:54:37 +00:00

tools

intel: Add meson option -Dintel-elk

2025-01-30 00:45:59 +00:00

vulkan

anv: xe: fully initialize drm_xe_sync addr/handle union

2025-02-02 21:34:45 -08:00

vulkan_hasvk

hasvk: disable logic op for float/srgb formats

2025-01-29 08:02:21 +00:00

meson.build

intel: Add meson option -Dintel-elk

2025-01-30 00:45:59 +00:00