Files
mesa/src
Samuel Pitoiset be81c8b8db radv: fix initializing the HTILE buffer on transfer queue
When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
2024-10-24 06:25:18 +00:00
..
2024-10-17 09:50:19 +00:00
2024-10-21 01:14:35 +00:00
2024-10-17 09:50:19 +00:00
2024-10-17 18:17:18 +00:00
2024-09-06 17:34:17 +00:00