Jason Ekstrand b39958a3a1 anv,nir: Move the ANV YCbCr lowering pass to common code ...

Nir changes:
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

Anv changes:

Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19950>

2023-01-16 14:10:21 +00:00

..

blorp

intel/blorp: Fix a hang caused by invalid dispatch enables on gfx7

2022-12-23 10:17:04 +00:00

ci

ci/iris: Add some recent flakes.

2023-01-04 21:18:08 +00:00

common

intel/common: Move i915 gem specific code to its own file

2022-12-23 18:22:29 +00:00

compiler

Revert "intel/compiler: fine-grained control of dispatch widths"

2023-01-12 00:33:25 +00:00

dev

Revert "intel/compiler: fine-grained control of dispatch widths"

2023-01-12 00:33:25 +00:00

ds

intel/utrace: document tracepoints

2023-01-13 01:22:15 +00:00

genxml

intel/genxml: Drop CACHE_MODE_SS definition.

2023-01-12 21:48:40 +00:00

isl

intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)

2022-12-15 11:43:00 -08:00

nullhw-layer

utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*

2022-11-02 07:25:39 +00:00

perf

intel: add MTL performance metrics

2022-12-09 09:13:02 +00:00

tools

anv,hasvk: migrate align32 to the right functions from util

2023-01-06 17:22:16 +00:00

vulkan

anv,nir: Move the ANV YCbCr lowering pass to common code

2023-01-16 14:10:21 +00:00

vulkan_hasvk

anv,hasvk: move the null check into the function call and drop null check copies

2023-01-06 17:22:16 +00:00

meson.build

intel: Disable SSE2 instruction set if building for non x86 architectures

2022-11-23 16:57:23 +00:00