Paulo Zanoni b4fef9a745 anv/trtt: also join the L3/L2 writes into a single MI_STORE_DATA_IMM ...

Same as the L1 case, but this one deals with 64bit entry addresses and
pte addresses.

Consecutive L3/L2 writes are much rarer than L1 writes since they
require some pretty big buffers, but we can still those cases in the
wild. I just don't think any change will be noticeable though.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25512>

2023-11-17 17:58:28 +00:00

..

blorp

anv/blorp: move helper function about BTI changes to blorp

2023-11-17 10:17:51 +00:00

ci

intel/ci: fix gl/vk dependencies in hsw jobs

2023-11-16 21:01:50 +00:00

common

intel/decoder: handle 3DPRIMITIVE_EXTENDED in accumulated prints

2023-11-17 10:17:51 +00:00

compiler

intel/nir/rt: fix reportIntersection() hitT handling

2023-11-17 07:06:30 +00:00

dev

intel/dev: use libdrm.h wrapper to support builds without libdrm

2023-11-17 07:38:33 +00:00

ds

intel/ds: use improved timestamp correlation if available

2023-11-09 13:22:49 +00:00

genxml

intel/genxml: add the Gen12+ TR-TT registers

2023-11-04 02:06:52 +00:00

isl

isl: disable MCS compression on R9G9B9E5

2023-11-09 20:20:43 +00:00

nullhw-layer

meson: support installation tags

2023-09-11 13:00:45 +00:00

perf

intel/dev: Rename mtl-p to mtl-h

2023-11-07 06:37:00 +00:00

tools

intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c

2023-09-06 01:39:53 +00:00

vulkan

anv/trtt: also join the L3/L2 writes into a single MI_STORE_DATA_IMM

2023-11-17 17:58:28 +00:00

vulkan_hasvk

intel/compiler: Remove unused parameter from brw_nir_analyze_ubo_ranges()

2023-11-08 18:10:31 +00:00

meson.build

intel: Only build perf if drivers or tools are enabled

2023-08-31 21:53:19 +00:00