a75c6163e6
This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <thomas.stellard@amd.com> Michel Dänzer <michel.daenzer@amd.com> Alex Deucher <alexander.deucher@amd.com> Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit96d882939dAuthor: Marek Olšák <maraeo@gmail.com> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commitbc1c836938Author: Marek Olšák <maraeo@gmail.com> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit04e3240087Author: Marek Olšák <maraeo@gmail.com> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commitc0c979eebcAuthor: Jerome Glisse <jglisse@redhat.com> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <jglisse@redhat.com> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit62f44f670bAuthor: Marek Olšák <maraeo@gmail.com> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit0950086376. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit9d9afcb5ba. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commitc2b800cf38. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit15146fd1bc. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit171be75522. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commitf183cc9ce3. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commita2361946e7. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit3d061caaed. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit669d8766ff. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit78293b99b2. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commite4340c1908. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits38bf276348andb0337b679a. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit8b4f7b0672. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit8cd03b933c. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit4445e170be.
598 lines
15 KiB
C++
598 lines
15 KiB
C++
//===-- AMDILMachineFunctionInfo.cpp - TODO: Add brief description -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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#include "AMDILMachineFunctionInfo.h"
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#include "AMDILCompilerErrors.h"
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#include "AMDILModuleInfo.h"
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#include "AMDILSubtarget.h"
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#include "AMDILTargetMachine.h"
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#include "AMDILUtilityFunctions.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Instructions.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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static const AMDILConstPtr *getConstPtr(const AMDILKernel *krnl, const std::string &arg) {
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llvm::SmallVector<AMDILConstPtr, DEFAULT_VEC_SLOTS>::const_iterator begin, end;
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for (begin = krnl->constPtr.begin(), end = krnl->constPtr.end();
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begin != end; ++begin) {
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if (!strcmp(begin->name.data(),arg.c_str())) {
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return &(*begin);
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}
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}
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return NULL;
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}
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void PrintfInfo::addOperand(size_t idx, uint32_t size) {
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mOperands.resize((unsigned)(idx + 1));
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mOperands[(unsigned)idx] = size;
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}
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uint32_t PrintfInfo::getPrintfID() {
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return mPrintfID;
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}
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void PrintfInfo::setPrintfID(uint32_t id) {
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mPrintfID = id;
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}
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size_t PrintfInfo::getNumOperands() {
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return mOperands.size();
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}
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uint32_t PrintfInfo::getOperandID(uint32_t idx) {
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return mOperands[idx];
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}
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AMDILMachineFunctionInfo::AMDILMachineFunctionInfo()
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: CalleeSavedFrameSize(0), BytesToPopOnReturn(0),
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DecorationStyle(None), ReturnAddrIndex(0),
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TailCallReturnAddrDelta(0),
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SRetReturnReg(0), UsesLDS(false), LDSArg(false),
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UsesGDS(false), GDSArg(false),
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mReservedLits(9)
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{
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for (uint32_t x = 0; x < AMDILDevice::MAX_IDS; ++x) {
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mUsedMem[x] = false;
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}
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mMF = NULL;
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mKernel = NULL;
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mScratchSize = -1;
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mArgSize = -1;
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mStackSize = -1;
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}
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AMDILMachineFunctionInfo::AMDILMachineFunctionInfo(MachineFunction& MF)
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: CalleeSavedFrameSize(0), BytesToPopOnReturn(0),
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DecorationStyle(None), ReturnAddrIndex(0),
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TailCallReturnAddrDelta(0),
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SRetReturnReg(0), UsesLDS(false), LDSArg(false),
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UsesGDS(false), GDSArg(false),
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mReservedLits(9)
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{
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for (uint32_t x = 0; x < AMDILDevice::MAX_IDS; ++x) {
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mUsedMem[x] = false;
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}
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const Function *F = MF.getFunction();
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mMF = &MF;
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MachineModuleInfo &mmi = MF.getMMI();
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const AMDILTargetMachine *TM =
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reinterpret_cast<const AMDILTargetMachine*>(&MF.getTarget());
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AMDILModuleInfo *AMI = &(mmi.getObjFileInfo<AMDILModuleInfo>());
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AMI->processModule(mmi.getModule(), TM);
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mSTM = TM->getSubtargetImpl();
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mKernel = AMI->getKernel(F->getName());
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mScratchSize = -1;
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mArgSize = -1;
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mStackSize = -1;
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}
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AMDILMachineFunctionInfo::~AMDILMachineFunctionInfo()
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{
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for (std::map<std::string, PrintfInfo*>::iterator pfb = printf_begin(),
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pfe = printf_end(); pfb != pfe; ++pfb) {
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delete pfb->second;
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}
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}
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unsigned int
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AMDILMachineFunctionInfo::getCalleeSavedFrameSize() const
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{
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return CalleeSavedFrameSize;
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}
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void
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AMDILMachineFunctionInfo::setCalleeSavedFrameSize(unsigned int bytes)
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{
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CalleeSavedFrameSize = bytes;
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}
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unsigned int
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AMDILMachineFunctionInfo::getBytesToPopOnReturn() const
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{
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return BytesToPopOnReturn;
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}
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void
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AMDILMachineFunctionInfo::setBytesToPopOnReturn(unsigned int bytes)
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{
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BytesToPopOnReturn = bytes;
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}
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NameDecorationStyle
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AMDILMachineFunctionInfo::getDecorationStyle() const
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{
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return DecorationStyle;
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}
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void
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AMDILMachineFunctionInfo::setDecorationStyle(NameDecorationStyle style)
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{
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DecorationStyle = style;
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}
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int
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AMDILMachineFunctionInfo::getRAIndex() const
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{
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return ReturnAddrIndex;
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}
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void
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AMDILMachineFunctionInfo::setRAIndex(int index)
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{
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ReturnAddrIndex = index;
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}
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int
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AMDILMachineFunctionInfo::getTCReturnAddrDelta() const
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{
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return TailCallReturnAddrDelta;
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}
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void
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AMDILMachineFunctionInfo::setTCReturnAddrDelta(int delta)
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{
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TailCallReturnAddrDelta = delta;
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}
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unsigned int
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AMDILMachineFunctionInfo::getSRetReturnReg() const
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{
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return SRetReturnReg;
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}
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void
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AMDILMachineFunctionInfo::setSRetReturnReg(unsigned int reg)
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{
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SRetReturnReg = reg;
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}
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void
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AMDILMachineFunctionInfo::setUsesLocal()
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{
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UsesLDS = true;
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}
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bool
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AMDILMachineFunctionInfo::usesLocal() const
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{
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return UsesLDS;
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}
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void
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AMDILMachineFunctionInfo::setHasLocalArg()
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{
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LDSArg = true;
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}
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bool
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AMDILMachineFunctionInfo::hasLocalArg() const
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{
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return LDSArg;
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}
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void
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AMDILMachineFunctionInfo::setUsesRegion()
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{
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UsesGDS = true;
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}
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bool
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AMDILMachineFunctionInfo::usesRegion() const
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{
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return UsesGDS;
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}
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void
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AMDILMachineFunctionInfo::setHasRegionArg()
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{
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GDSArg = true;
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}
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bool
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AMDILMachineFunctionInfo::hasRegionArg() const
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{
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return GDSArg;
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}
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bool
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AMDILMachineFunctionInfo::usesHWConstant(std::string name) const
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{
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const AMDILConstPtr *curConst = getConstPtr(mKernel, name);
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if (curConst) {
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return curConst->usesHardware;
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} else {
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return false;
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}
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}
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uint32_t
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AMDILMachineFunctionInfo::getLocal(uint32_t dim)
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{
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if (mKernel && mKernel->sgv) {
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AMDILKernelAttr *sgv = mKernel->sgv;
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switch (dim) {
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default: break;
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case 0:
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case 1:
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case 2:
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return sgv->reqGroupSize[dim];
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break;
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case 3:
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return sgv->reqGroupSize[0] * sgv->reqGroupSize[1] * sgv->reqGroupSize[2];
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};
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}
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switch (dim) {
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default:
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return 1;
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case 3:
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return mSTM->getDefaultSize(0) *
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mSTM->getDefaultSize(1) *
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mSTM->getDefaultSize(2);
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case 2:
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case 1:
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case 0:
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return mSTM->getDefaultSize(dim);
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break;
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};
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return 1;
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}
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bool
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AMDILMachineFunctionInfo::isKernel() const
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{
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return mKernel != NULL && mKernel->mKernel;
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}
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AMDILKernel*
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AMDILMachineFunctionInfo::getKernel()
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{
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return mKernel;
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}
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std::string
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AMDILMachineFunctionInfo::getName()
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{
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if (mMF) {
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return mMF->getFunction()->getName();
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} else {
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return "";
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}
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}
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uint32_t
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AMDILMachineFunctionInfo::getArgSize()
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{
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if (mArgSize == -1) {
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Function::const_arg_iterator I = mMF->getFunction()->arg_begin();
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Function::const_arg_iterator Ie = mMF->getFunction()->arg_end();
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uint32_t Counter = 0;
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while (I != Ie) {
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Type* curType = I->getType();
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if (curType->isIntegerTy() || curType->isFloatingPointTy()) {
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++Counter;
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} else if (const VectorType *VT = dyn_cast<VectorType>(curType)) {
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Type *ET = VT->getElementType();
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int numEle = VT->getNumElements();
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switch (ET->getPrimitiveSizeInBits()) {
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default:
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if (numEle == 3) {
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Counter++;
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} else {
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Counter += ((numEle + 2) >> 2);
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}
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break;
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case 64:
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if (numEle == 3) {
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Counter += 2;
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} else {
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Counter += (numEle >> 1);
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}
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break;
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case 16:
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case 8:
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switch (numEle) {
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default:
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Counter += ((numEle + 2) >> 2);
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case 2:
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Counter++;
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break;
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}
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break;
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}
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} else if (const PointerType *PT = dyn_cast<PointerType>(curType)) {
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Type *CT = PT->getElementType();
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const StructType *ST = dyn_cast<StructType>(CT);
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if (ST && ST->isOpaque()) {
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bool i1d = ST->getName() == "struct._image1d_t";
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bool i1da = ST->getName() == "struct._image1d_array_t";
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bool i1db = ST->getName() == "struct._image1d_buffer_t";
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bool i2d = ST->getName() == "struct._image2d_t";
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bool i2da = ST->getName() == "struct._image2d_array_t";
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bool i3d = ST->getName() == "struct._image3d_t";
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bool is_image = i1d || i1da || i1db || i2d || i2da || i3d;
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if (is_image) {
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if (mSTM->device()->isSupported(AMDILDeviceInfo::Images)) {
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Counter += 2;
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} else {
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addErrorMsg(amd::CompilerErrorMessage[NO_IMAGE_SUPPORT]);
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}
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} else {
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Counter++;
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}
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} else if (CT->isStructTy()
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&& PT->getAddressSpace() == AMDILAS::PRIVATE_ADDRESS) {
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StructType *ST = dyn_cast<StructType>(CT);
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Counter += ((getTypeSize(ST) + 15) & ~15) >> 4;
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} else if (CT->isIntOrIntVectorTy()
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|| CT->isFPOrFPVectorTy()
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|| CT->isArrayTy()
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|| CT->isPointerTy()
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|| PT->getAddressSpace() != AMDILAS::PRIVATE_ADDRESS) {
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++Counter;
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} else {
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assert(0 && "Current type is not supported!");
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addErrorMsg(amd::CompilerErrorMessage[INTERNAL_ERROR]);
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}
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} else {
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assert(0 && "Current type is not supported!");
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addErrorMsg(amd::CompilerErrorMessage[INTERNAL_ERROR]);
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}
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++I;
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}
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// Convert from slots to bytes by multiplying by 16(shift by 4).
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mArgSize = Counter << 4;
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}
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return (uint32_t)mArgSize;
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}
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uint32_t
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AMDILMachineFunctionInfo::getScratchSize()
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{
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if (mScratchSize == -1) {
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mScratchSize = 0;
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Function::const_arg_iterator I = mMF->getFunction()->arg_begin();
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Function::const_arg_iterator Ie = mMF->getFunction()->arg_end();
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while (I != Ie) {
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Type *curType = I->getType();
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mScratchSize += ((getTypeSize(curType) + 15) & ~15);
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++I;
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}
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mScratchSize += ((mScratchSize + 15) & ~15);
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}
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return (uint32_t)mScratchSize;
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}
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uint32_t
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AMDILMachineFunctionInfo::getStackSize()
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{
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if (mStackSize == -1) {
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uint32_t privSize = 0;
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const MachineFrameInfo *MFI = mMF->getFrameInfo();
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privSize = MFI->getOffsetAdjustment() + MFI->getStackSize();
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const AMDILTargetMachine *TM =
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reinterpret_cast<const AMDILTargetMachine*>(&mMF->getTarget());
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bool addStackSize = TM->getOptLevel() == CodeGenOpt::None;
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Function::const_arg_iterator I = mMF->getFunction()->arg_begin();
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Function::const_arg_iterator Ie = mMF->getFunction()->arg_end();
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while (I != Ie) {
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Type *curType = I->getType();
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++I;
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if (dyn_cast<PointerType>(curType)) {
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Type *CT = dyn_cast<PointerType>(curType)->getElementType();
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if (CT->isStructTy()
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&& dyn_cast<PointerType>(curType)->getAddressSpace()
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== AMDILAS::PRIVATE_ADDRESS) {
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addStackSize = true;
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}
|
|
}
|
|
}
|
|
if (addStackSize) {
|
|
privSize += getScratchSize();
|
|
}
|
|
mStackSize = privSize;
|
|
}
|
|
return (uint32_t)mStackSize;
|
|
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addi32Literal(uint32_t val, int Opcode) {
|
|
// Since we have emulated 16/8/1 bit register types with a 32bit real
|
|
// register, we need to sign extend the constants to 32bits in order for
|
|
// comparisons against the constants to work correctly, this fixes some issues
|
|
// we had in conformance failing for saturation.
|
|
if (Opcode == AMDIL::LOADCONST_i16) {
|
|
val = (((int32_t)val << 16) >> 16);
|
|
} else if (Opcode == AMDIL::LOADCONST_i8) {
|
|
val = (((int32_t)val << 24) >> 24);
|
|
}
|
|
if (mIntLits.find(val) == mIntLits.end()) {
|
|
mIntLits[val] = getNumLiterals();
|
|
}
|
|
return mIntLits[val];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addi64Literal(uint64_t val) {
|
|
if (mLongLits.find(val) == mLongLits.end()) {
|
|
mLongLits[val] = getNumLiterals();
|
|
}
|
|
return mLongLits[val];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addi128Literal(uint64_t val_lo, uint64_t val_hi) {
|
|
std::pair<uint64_t, uint64_t> a;
|
|
a.first = val_lo;
|
|
a.second = val_hi;
|
|
if (mVecLits.find(a) == mVecLits.end()) {
|
|
mVecLits[a] = getNumLiterals();
|
|
}
|
|
return mVecLits[a];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addf32Literal(const ConstantFP *CFP) {
|
|
uint32_t val = (uint32_t)CFP->getValueAPF().bitcastToAPInt().getZExtValue();
|
|
if (mIntLits.find(val) == mIntLits.end()) {
|
|
mIntLits[val] = getNumLiterals();
|
|
}
|
|
return mIntLits[val];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addf64Literal(const ConstantFP *CFP) {
|
|
union dtol_union {
|
|
double d;
|
|
uint64_t ul;
|
|
} dval;
|
|
const APFloat &APF = CFP->getValueAPF();
|
|
if (&APF.getSemantics() == (const llvm::fltSemantics *)&APFloat::IEEEsingle) {
|
|
float fval = APF.convertToFloat();
|
|
dval.d = (double)fval;
|
|
} else {
|
|
dval.d = APF.convertToDouble();
|
|
}
|
|
if (mLongLits.find(dval.ul) == mLongLits.end()) {
|
|
mLongLits[dval.ul] = getNumLiterals();
|
|
}
|
|
return mLongLits[dval.ul];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::getIntLits(uint32_t offset)
|
|
{
|
|
return mIntLits[offset];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::getLongLits(uint64_t offset)
|
|
{
|
|
return mLongLits[offset];
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::getVecLits(uint64_t low64, uint64_t high64)
|
|
{
|
|
return mVecLits[std::pair<uint64_t, uint64_t>(low64, high64)];
|
|
}
|
|
|
|
size_t
|
|
AMDILMachineFunctionInfo::getNumLiterals() const {
|
|
return mLongLits.size() + mIntLits.size() + mVecLits.size() + mReservedLits;
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::addReservedLiterals(uint32_t size)
|
|
{
|
|
mReservedLits += size;
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addSampler(std::string name, uint32_t val)
|
|
{
|
|
if (mSamplerMap.find(name) != mSamplerMap.end()) {
|
|
SamplerInfo newVal = mSamplerMap[name];
|
|
assert(newVal.val == val
|
|
&& "Found a sampler with same name but different values!");
|
|
return mSamplerMap[name].idx;
|
|
} else {
|
|
SamplerInfo curVal;
|
|
curVal.name = name;
|
|
curVal.val = val;
|
|
curVal.idx = mSamplerMap.size();
|
|
mSamplerMap[name] = curVal;
|
|
return curVal.idx;
|
|
}
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::setUsesMem(unsigned id) {
|
|
assert(id < AMDILDevice::MAX_IDS &&
|
|
"Must set the ID to be less than MAX_IDS!");
|
|
mUsedMem[id] = true;
|
|
}
|
|
|
|
bool
|
|
AMDILMachineFunctionInfo::usesMem(unsigned id) {
|
|
assert(id < AMDILDevice::MAX_IDS &&
|
|
"Must set the ID to be less than MAX_IDS!");
|
|
return mUsedMem[id];
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::addErrorMsg(const char *msg, ErrorMsgEnum val)
|
|
{
|
|
if (val == DEBUG_ONLY) {
|
|
#if defined(DEBUG) || defined(_DEBUG)
|
|
mErrors.insert(msg);
|
|
#endif
|
|
} else if (val == RELEASE_ONLY) {
|
|
#if !defined(DEBUG) && !defined(_DEBUG)
|
|
mErrors.insert(msg);
|
|
#endif
|
|
} else if (val == ALWAYS) {
|
|
mErrors.insert(msg);
|
|
}
|
|
}
|
|
|
|
uint32_t
|
|
AMDILMachineFunctionInfo::addPrintfString(std::string &name, unsigned offset)
|
|
{
|
|
if (mPrintfMap.find(name) != mPrintfMap.end()) {
|
|
return mPrintfMap[name]->getPrintfID();
|
|
} else {
|
|
PrintfInfo *info = new PrintfInfo;
|
|
info->setPrintfID(mPrintfMap.size() + offset);
|
|
mPrintfMap[name] = info;
|
|
return info->getPrintfID();
|
|
}
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::addPrintfOperand(std::string &name,
|
|
size_t idx,
|
|
uint32_t size)
|
|
{
|
|
mPrintfMap[name]->addOperand(idx, size);
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::addMetadata(const char *md, bool kernelOnly)
|
|
{
|
|
addMetadata(std::string(md), kernelOnly);
|
|
}
|
|
|
|
void
|
|
AMDILMachineFunctionInfo::addMetadata(std::string md, bool kernelOnly)
|
|
{
|
|
if (kernelOnly) {
|
|
mMetadataKernel.push_back(md);
|
|
} else {
|
|
mMetadataFunc.insert(md);
|
|
}
|
|
}
|
|
|