Samuel Pitoiset a652c1653a radv: introduce new radv_pipeline_stage structure ...

This is used to store everything for a pipeline stage like the module,
the NIR, the shader arguments etc. This is inspired from ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15794>

2022-04-08 16:38:30 +00:00

..

addrlib

amd: update addrlib

2022-03-01 17:03:00 +00:00

ci

radv/ci: update CI lists against CTS 1.3.1.1

2022-04-05 09:13:41 +02:00

common

amd: Fix ac_gpu_info.c compilation on windows

2022-03-24 09:11:13 +00:00

compiler

aco: do not use designated initializers

2022-04-05 16:58:56 +00:00

drm-shim

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00

llvm

ac: remove LLVM 4.0 workaround

2022-03-31 10:15:19 +00:00

registers

amd: remove the _UMD suffix from register definitions

2022-02-22 11:41:04 +00:00

vulkan

radv: introduce new radv_pipeline_stage structure

2022-04-08 16:38:30 +00:00

.clang-format

radv, aco: Add u_foreach_bit to .clang-format.

2022-02-22 14:57:29 +00:00

meson.build

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00