Tom Stellard
71 lines
1.9 KiB
C++
71 lines
1.9 KiB
C++
//===-- SIPropagateImmReads.cpp - TODO: Add brief description -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TODO: Add full description
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUUtil.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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namespace {
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class SIPropagateImmReadsPass : public MachineFunctionPass {
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private:
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static char ID;
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TargetMachine &TM;
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public:
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SIPropagateImmReadsPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TM(tm) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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};
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} /* End anonymous namespace */
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char SIPropagateImmReadsPass::ID = 0;
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FunctionPass *llvm::createSIPropagateImmReadsPass(TargetMachine &tm) {
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return new SIPropagateImmReadsPass(tm);
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}
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bool SIPropagateImmReadsPass::runOnMachineFunction(MachineFunction &MF)
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{
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const SIInstrInfo * TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
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I != MBB.end(); I = Next, Next = llvm::next(I)) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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case AMDIL::LOADCONST_f32:
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case AMDIL::LOADCONST_i32:
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break;
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default:
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continue;
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}
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/* XXX: Create and use S_MOV_IMM for SREGs */
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
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.addOperand(MI.getOperand(0))
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.addOperand(MI.getOperand(1));
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MI.eraseFromParent();
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}
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}
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return false;
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}
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