0b3871bc7f
We allocate GGTT entries and physical addresses are we create engines rather than having a fixed layout. Context images now receive a parameter argument which is used to setup pml4 & ring buffer addresses. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
105 lines
3.8 KiB
C
105 lines
3.8 KiB
C
/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef GEN_CONTEXT_H
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#define GEN_CONTEXT_H
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#include <stdint.h>
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#define RING_SIZE (1 * 4096)
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#define PPHWSP_SIZE (1 * 4096)
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#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * 4096)
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#define GEN10_LR_CONTEXT_RENDER_SIZE (19 * 4096)
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
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#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
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#define CONTEXT_RENDER_SIZE GEN9_LR_CONTEXT_RENDER_SIZE /* largest size */
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#define CONTEXT_OTHER_SIZE GEN8_LR_CONTEXT_OTHER_SIZE
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#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
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#define MI_LRI_FORCE_POSTED (1<<12)
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#define MI_BATCH_BUFFER_END (0xA << 23)
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#define HWS_PGA_RCSUNIT 0x02080
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#define HWS_PGA_VCSUNIT0 0x12080
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#define HWS_PGA_BCSUNIT 0x22080
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#define GFX_MODE_RCSUNIT 0x0229c
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#define GFX_MODE_VCSUNIT0 0x1229c
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#define GFX_MODE_BCSUNIT 0x2229c
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#define EXECLIST_SUBMITPORT_RCSUNIT 0x02230
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#define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230
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#define EXECLIST_SUBMITPORT_BCSUNIT 0x22230
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#define EXECLIST_STATUS_RCSUNIT 0x02234
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#define EXECLIST_STATUS_VCSUNIT0 0x12234
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#define EXECLIST_STATUS_BCSUNIT 0x22234
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#define EXECLIST_SQ_CONTENTS0_RCSUNIT 0x02510
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#define EXECLIST_SQ_CONTENTS0_VCSUNIT0 0x12510
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#define EXECLIST_SQ_CONTENTS0_BCSUNIT 0x22510
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#define EXECLIST_CONTROL_RCSUNIT 0x02550
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#define EXECLIST_CONTROL_VCSUNIT0 0x12550
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#define EXECLIST_CONTROL_BCSUNIT 0x22550
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#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
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#define PTE_SIZE 4
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#define GEN8_PTE_SIZE 8
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#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
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#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
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#define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |
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* PPGTT Enabled |
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* Legacy Context with 64 bit VA support |
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* Valid
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*/
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#define MI_LOAD_REGISTER_IMM_vals(data, flags, ...) do { \
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uint32_t __regs[] = { __VA_ARGS__ }; \
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assert((ARRAY_SIZE(__regs) % 2) == 0); \
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*(data)++ = MI_LOAD_REGISTER_IMM_n(ARRAY_SIZE(__regs) / 2) | (flags); \
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for (unsigned __e = 0; __e < ARRAY_SIZE(__regs); __e++) \
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*(data)++ = __regs[__e]; \
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} while (0)
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struct gen_context_parameters {
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uint64_t pml4_addr;
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uint64_t ring_addr;
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uint32_t ring_size;
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};
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typedef void (*gen_context_init_t)(const struct gen_context_parameters *, uint32_t *, uint32_t *);
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#include "gen8_context.h"
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#include "gen10_context.h"
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#endif /* GEN_CONTEXT_H */
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