Eric R. Smith
03a1a5009f
The ATEST instruction needs sample_mask as an input, but if the shader writes to color before sample_mask we could emit them in the wrong order. Fix this in pan_nir_lower_zs_store by deferring the color write until after the sample_mask write. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Benjamin Lee <benjamin.lee@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32879>
239 lines
8.2 KiB
C
239 lines
8.2 KiB
C
/*
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* Copyright (C) 2018-2020 Collabora, Ltd.
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* Copyright (C) 2019-2020 Icecream95
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler/nir/nir_builder.h"
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#include "pan_ir.h"
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/* Midgard can write all of color, depth and stencil in a single writeout
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* operation, so we merge depth/stencil stores with color stores.
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* If there are no color stores, we add a write to the "depth RT".
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*
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* For Bifrost, we want these combined so we can properly order
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* +ZS_EMIT with respect to +ATEST and +BLEND, as well as combining
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* depth/stencil stores into a single +ZS_EMIT op.
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*/
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/*
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* Get the type to report for a piece of a combined store, given the store it
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* is combining from. If there is no store to render target #0, a dummy <0.0,
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* 0.0, 0.0, 0.0> write is used, so report a matching float32 type.
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*/
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static nir_alu_type
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pan_nir_rt_store_type(nir_intrinsic_instr *store)
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{
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return store ? nir_intrinsic_src_type(store) : nir_type_float32;
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}
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static void
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pan_nir_emit_combined_store(nir_builder *b, nir_intrinsic_instr *rt0_store,
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unsigned writeout, nir_intrinsic_instr **stores)
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{
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nir_intrinsic_instr *intr = nir_intrinsic_instr_create(
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b->shader, nir_intrinsic_store_combined_output_pan);
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intr->num_components = rt0_store ? rt0_store->src[0].ssa->num_components : 4;
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if (rt0_store)
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nir_intrinsic_set_io_semantics(intr,
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nir_intrinsic_io_semantics(rt0_store));
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nir_intrinsic_set_src_type(intr, pan_nir_rt_store_type(rt0_store));
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nir_intrinsic_set_dest_type(intr, pan_nir_rt_store_type(stores[2]));
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nir_intrinsic_set_component(intr, writeout);
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nir_def *zero = nir_imm_int(b, 0);
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nir_def *zero4 = nir_imm_ivec4(b, 0, 0, 0, 0);
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nir_def *src[] = {
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rt0_store ? rt0_store->src[0].ssa : zero4,
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rt0_store ? rt0_store->src[1].ssa : zero,
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stores[0] ? stores[0]->src[0].ssa : zero,
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stores[1] ? stores[1]->src[0].ssa : zero,
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stores[2] ? stores[2]->src[0].ssa : zero4,
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};
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for (int i = 0; i < ARRAY_SIZE(src); ++i)
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intr->src[i] = nir_src_for_ssa(src[i]);
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nir_builder_instr_insert(b, &intr->instr);
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}
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static bool
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kill_depth_stencil_writes(nir_builder *b, nir_intrinsic_instr *intr,
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UNUSED void *data)
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{
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if (intr->intrinsic != nir_intrinsic_store_output)
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return false;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (sem.location != FRAG_RESULT_DEPTH && sem.location != FRAG_RESULT_STENCIL)
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return false;
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nir_instr_remove(&intr->instr);
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return true;
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}
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bool
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pan_nir_lower_zs_store(nir_shader *nir)
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{
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bool progress = false;
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if (nir->info.stage != MESA_SHADER_FRAGMENT)
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return false;
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/* Remove all stencil/depth writes if early fragment test is forced. */
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if (nir->info.fs.early_fragment_tests)
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progress |= nir_shader_intrinsics_pass(nir, kill_depth_stencil_writes,
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nir_metadata_control_flow, NULL);
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nir_foreach_function_impl(impl, nir) {
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nir_intrinsic_instr *stores[3] = {NULL};
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nir_intrinsic_instr *last_mask_store = NULL;
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nir_block *mask_block = NULL;
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unsigned writeout = 0;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (sem.location == FRAG_RESULT_DEPTH) {
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stores[0] = intr;
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writeout |= PAN_WRITEOUT_Z;
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} else if (sem.location == FRAG_RESULT_STENCIL) {
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stores[1] = intr;
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writeout |= PAN_WRITEOUT_S;
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} else if (sem.dual_source_blend_index) {
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assert(!stores[2]); /* there should be only 1 source for dual blending */
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stores[2] = intr;
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writeout |= PAN_WRITEOUT_2;
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} else if (sem.location == FRAG_RESULT_SAMPLE_MASK) {
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last_mask_store = intr;
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mask_block = intr->instr.block;
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}
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}
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}
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if (!writeout && !last_mask_store)
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continue;
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nir_block *common_block = mask_block;
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/* Ensure all stores are in the same block */
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for (unsigned i = 0; i < ARRAY_SIZE(stores); ++i) {
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if (!stores[i])
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continue;
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nir_block *block = stores[i]->instr.block;
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if (common_block)
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assert(common_block == block);
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else
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common_block = block;
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}
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/* move data stores in the common block to after the last mask store */
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if (last_mask_store) {
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nir_cursor insert_point = nir_after_instr(&last_mask_store->instr);
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nir_foreach_instr_safe(instr, mask_block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* stop when we've reached the last store to mask */
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if (intr == last_mask_store)
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break;
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (sem.location >= FRAG_RESULT_DATA0 &&
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sem.location <= FRAG_RESULT_DATA7) {
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nir_instr_move(insert_point, instr);
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insert_point = nir_after_instr(instr);
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}
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}
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}
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bool replaced = false;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (sem.location < FRAG_RESULT_DATA0)
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continue;
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if (sem.dual_source_blend_index)
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continue;
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assert(nir_src_is_const(intr->src[1]) && "no indirect outputs");
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nir_builder b =
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nir_builder_at(nir_after_block_before_jump(instr->block));
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/* Trying to write depth twice results in the
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* wrong blend shader being executed on
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* Midgard */
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unsigned this_store = PAN_WRITEOUT_C | (replaced ? 0 : writeout);
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pan_nir_emit_combined_store(&b, intr, this_store, stores);
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nir_instr_remove(instr);
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replaced = true;
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}
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}
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/* Insert a store to the depth RT (0xff) if needed */
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if (!replaced) {
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nir_builder b =
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nir_builder_at(nir_after_block_before_jump(common_block));
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pan_nir_emit_combined_store(&b, NULL, writeout, stores);
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}
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for (unsigned i = 0; i < ARRAY_SIZE(stores); ++i) {
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if (stores[i])
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nir_instr_remove(&stores[i]->instr);
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}
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nir_metadata_preserve(impl,
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nir_metadata_control_flow);
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progress = true;
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}
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return progress;
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}
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