Lionel Landwerlin e666089082 intel/disasm: add missing handling of <1;1,0> ...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7cd9adeb41 ("intel/compiler: In XeHP prefer <1;1,0> regions before compacting")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16704>

2022-05-26 06:42:16 +00:00

..

blorp

nir/builder: Add a nir_trim_vector helper

2022-05-11 14:47:33 +00:00

ci

ci/iris: skqp: remove flaking atlastext for TGL

2022-05-17 06:57:19 +00:00

common

intel/decoder: Fix binding table pointer decoding with large offsets

2022-05-17 08:52:00 +00:00

compiler

intel/disasm: add missing handling of <1;1,0>

2022-05-26 06:42:16 +00:00

dev

intel/dev: Enable first set of DG2 PCI IDs

2022-05-12 03:03:57 -07:00

ds

u_trace/anv/iris: drop cs argument for recording traces

2022-05-19 19:04:28 +00:00

genxml

intel/genxml: Add SAMPLER_MODE bits for enabling Small PL on Icelake

2022-04-11 19:17:07 +00:00

isl

isl,iris: Add DG2 CCS modifier support for XeHP

2022-04-28 20:02:14 +00:00

nullhw-layer

vulkan: drop empty vulkan_wsi_args

2022-04-27 11:51:26 +00:00

perf

intel/perf: deal with OA reports timestamp values on DG2

2022-05-17 19:55:10 +00:00

tools

intel/tools: fix 32-bit build

2022-05-24 18:27:32 +00:00

vulkan

anv: Update line range

2022-05-24 23:09:26 +00:00

Makefile.perf.am

intel: Rename GEN_PERF prefix to INTEL_PERF in build files

2021-04-20 20:06:34 +00:00

meson.build

anv: add perfetto source

2022-01-14 20:17:44 +00:00