Files
mesa/src/amd/vulkan/nir/radv_nir_opt_fs_builtins.c
T
Konstantin Seurer af375c6756 radv: Optimize fs builtins using static gfx state
The values of some builtins are known at compile time when the
application creates pipelines with static state.

Stats for graphics pipelines:

Totals from 568 (0.71% of 80536) affected shaders:
MaxWaves: 12364 -> 12502 (+1.12%); split: +1.26%, -0.15%
Instrs: 515696 -> 501182 (-2.81%); split: -2.85%, +0.04%
CodeSize: 2815736 -> 2741464 (-2.64%); split: -2.69%, +0.05%
VGPRs: 29528 -> 29160 (-1.25%); split: -1.71%, +0.46%
SpillSGPRs: 212 -> 215 (+1.42%)
Latency: 5515421 -> 5409125 (-1.93%); split: -2.05%, +0.13%
InvThroughput: 1293512 -> 1277913 (-1.21%); split: -1.27%, +0.06%
VClause: 10570 -> 10295 (-2.60%); split: -2.74%, +0.14%
SClause: 19040 -> 18531 (-2.67%); split: -2.83%, +0.16%
Copies: 37189 -> 35431 (-4.73%); split: -5.31%, +0.58%
Branches: 11391 -> 11070 (-2.82%); split: -2.92%, +0.11%
PreSGPRs: 27848 -> 27313 (-1.92%); split: -1.95%, +0.03%
PreVGPRs: 24847 -> 24106 (-2.98%); split: -3.00%, +0.02%
VALU: 359356 -> 348779 (-2.94%); split: -2.97%, +0.03%
SALU: 59135 -> 57448 (-2.85%); split: -3.11%, +0.26%
VMEM: 14674 -> 14313 (-2.46%)
SMEM: 30901 -> 30342 (-1.81%); split: -1.84%, +0.03%

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32793>
2025-02-17 09:45:15 +00:00

43 lines
1.2 KiB
C

/*
* Copyright © 2025 Valve Corporation
*
* SPDX-License-Identifier: MIT
*/
#include "nir/nir.h"
#include "nir/nir_builder.h"
#include "radv_nir.h"
#include "radv_pipeline_graphics.h"
static bool
pass(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{
const struct radv_graphics_state_key *gfx_state = data;
b->cursor = nir_before_instr(&intr->instr);
nir_def *replacement = NULL;
if (intr->intrinsic == nir_intrinsic_load_front_face) {
if (gfx_state->rs.cull_mode == VK_CULL_MODE_FRONT_BIT) {
replacement = nir_imm_false(b);
} else if (gfx_state->rs.cull_mode == VK_CULL_MODE_BACK_BIT) {
replacement = nir_imm_true(b);
}
} else if (intr->intrinsic == nir_intrinsic_load_sample_id) {
if (!gfx_state->dynamic_rasterization_samples && gfx_state->ms.rasterization_samples == 0) {
replacement = nir_imm_intN_t(b, 0, intr->def.bit_size);
}
}
if (!replacement)
return false;
nir_def_replace(&intr->def, replacement);
return true;
}
bool
radv_nir_opt_fs_builtins(nir_shader *shader, const struct radv_graphics_state_key *gfx_state)
{
return nir_shader_intrinsics_pass(shader, pass, nir_metadata_control_flow, (void *)gfx_state);
}