mesa/src/intel at 792d77165be40691d0c3b6dc025a792cb076109e - mesa

Files

T

Lionel Landwerlin 792d77165b aubinator: add a custom handler for immediate register load

Transforming this :

0x00c77084:  0x11000001:  MI_LOAD_REGISTER_IMM
0x00c77088:  0x0000b020 : Dword 1
    Register Offset: 0x0000b020
    0x00c7708c:  0x00880038 : Dword 2
    Data DWord: 8912952

Into this:

0x007880f0:  0x11000001:  MI_LOAD_REGISTER_IMM
0x007880f4:  0x0000b020 : Dword 1
    Register Offset: 0x0000b020
    0x007880f8:  0x00080040 : Dword 2
    Data DWord: 524352
register L3CNTLREG2 (0xb020) : 0x80040
    SLM Enable: 0
    URB Allocation: 32
    URB Low Bandwidth: 0
    RO Allocation: 32
    RO Low Bandwidth: 0
    DC Allocation: 0
    DC Low Bandwidth: 0

v2: Drop unused arguments (Sirisha)
    Print out register name

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

2016-09-20 10:47:21 +01:00

blorp

nir: Add a flag to lower_io to force "sample" interpolation

2016-09-15 13:31:43 -07:00

common

intel: Move Vulkan sample positions to common code

2016-09-14 17:51:16 -07:00

genxml

anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW

2016-09-14 17:53:16 -07:00

isl

isl: Finish tiling filtering for Gen6.