75e68f44af
Our I/O lowering doesn't handle 64-bit TCS stores and TES loads which use several slots. Because of the large stride between slots, we have to split the load so that there's a single load_buffer_amd/store_buffer_amd intrinsic for each slot. Our I/O lowering also sometimes creates nir_op_pack_64_2x32 after nir_lower_alu_to_scalar. Fixes KHR-GL45.gpu_shader_fp64.fp64.varyings with Zink (https://gitlab.freedesktop.org/mesa/mesa/-/issues/6276) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15863>