Rohan Garg db6aaa691d intel/compiler: infer the number of operands using lsc_op_num_data_values ...

nir_emit_global_atomic should utilize lsc_op_num_data_values to
infer the number of operands for global atomic ops, following the same
pattern as nir_emit_surface_atomic

Fixes: 90a2137 ('intel/compiler: Use LSC opcode enum rather than legacy BRW_AOPs')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26432>

2023-12-07 14:40:24 +00:00

..

blorp

blorp: Handle stencil buffer compression on blitter engine

2023-12-06 04:39:09 +00:00

ci

intel/ci: run only the relevant jobs when changing the ci expectations

2023-12-07 09:59:39 +00:00

common

intel: Sync xe_drm.h take 2 part 3

2023-12-06 17:35:23 +00:00

compiler

intel/compiler: infer the number of operands using lsc_op_num_data_values

2023-12-07 14:40:24 +00:00

dev

intel: Sync xe_drm.h take 2 part 3

2023-12-06 17:35:23 +00:00

ds

intel/ds: add trace of buffer markers

2023-11-29 01:16:22 +00:00

genxml

intel/genxml/xe2: Update PIPELINE_SELECT

2023-12-07 14:16:18 +00:00

isl

intel: Generate source file with utf-8 encoding from mako template

2023-12-07 12:41:07 +00:00

nullhw-layer

meson: support installation tags

2023-09-11 13:00:45 +00:00

perf

intel: Remove unused ALIGN macro

2023-12-07 02:30:53 +00:00

tools

intel/tools: 32bit compile fixes

2023-12-05 17:45:18 +00:00

vulkan

intel/genxml/xe2: Update PIPELINE_SELECT

2023-12-07 14:16:18 +00:00

vulkan_hasvk

treewide: Avoid use align as variable, replace it with other names

2023-12-07 02:30:53 +00:00

meson.build

intel: Only build perf if drivers or tools are enabled

2023-08-31 21:53:19 +00:00