b18e68fc25
According to the simulator a cacheline of the blend state cache corresponds to 3 cachelines of L3 that are always filled regardless of the number of render targets in use. Allocate enough space to avoid pagefaults under simulation, since a scratch page isn't bound by default. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>