Marek Olšák 39800f0fa3 amd: change chip_class naming to "enum amd_gfx_level gfx_level" ...

This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>

2022-05-13 14:56:22 -04:00

..

addrlib

amd: add chip identification for gfx1100-1103

2022-05-10 04:29:55 +00:00

ci

radv/ci: reduce the execution timeout

2022-05-13 13:30:48 +00:00

common

amd: change chip_class naming to "enum amd_gfx_level gfx_level"

2022-05-13 14:56:22 -04:00

compiler

amd: change chip_class naming to "enum amd_gfx_level gfx_level"

2022-05-13 14:56:22 -04:00

drm-shim

Use proper types for meson objects

2022-04-18 13:03:08 +03:00

llvm

amd: change chip_class naming to "enum amd_gfx_level gfx_level"

2022-05-13 14:56:22 -04:00

registers

amd: change chip_class naming to "enum amd_gfx_level gfx_level"

2022-05-13 14:56:22 -04:00

vulkan

amd: change chip_class naming to "enum amd_gfx_level gfx_level"

2022-05-13 14:56:22 -04:00

.clang-format

radv: allow holes in inline push constants

2022-04-12 11:44:30 +00:00

meson.build

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00