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So for this entry we want the CPU mapping to be WC but GPU caches can be WB. This way GPU don't need to snoop to CPU caches and at the end of workloads L3 cache is flushed, so CPU access is coherent after get the signal that workload was finished. With this the transient(XD) L3 flushes will only affect displayable buffers. Ref: Bspec 71582 (r59285) Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>