23bd356b42
If the (NIR) destination is a register (i.e., not an SSA value), the destination of the BRW instruction will not be is_scalar. This occurs in some shaders in Final Fantasy XVI (and finalfantasytype0_1.rdc.2826e29da3722a83.1.foz). If the destination is not is_scalar, revert most of this code to the state previous tof3593df877. This means - Allocate a SIMD1 register and UNDEF it. - Emit a SIMD1 MOV_RELOC_IMM to that register. - Emit an additional MOV to expand the SIMD1 result. Closes: #12520 Fixes:f3593df877("brw/nir: Treat load_reloc_const_intel as convergent") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37384>