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5c362cde33b9f3e76bb032112a91fcb761df490c
mesa/src/amd
T
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Daniel Schürmann 5c362cde33 radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22267>
2023-04-04 18:35:43 +00:00
..
addrlib
amd: update addrlib
2023-03-29 20:36:09 +00:00
ci
Uprev Piglit to 2391a83d1639a7ab7bbea02853b922878687b0e5
2023-04-04 15:37:14 +00:00
common
ac/nir: add ac_nir_load_arg_at_offset
2023-04-03 01:35:06 +00:00
compiler
aco: don't use shared VGPRs for shaders consisting of multiple binaries
2023-04-04 18:35:43 +00:00
drm-shim
r300: use drm_shim_override
2022-11-16 14:37:47 +00:00
llvm
ac/llvm: remove ac_build_opencoded_load_format
2023-04-03 01:35:06 +00:00
registers
amd/registers: only define SPI and COMPUTE registers in the 0xB000 range
2023-02-24 21:27:24 +00:00
vulkan
radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs
2023-04-04 18:35:43 +00:00
.clang-format
amd: Add radv_foreach_stage to ForEachMacros.
2023-03-27 08:29:35 +00:00
meson.build
meson: build radeon drm-shim also for r300 and r600
2022-11-16 14:37:47 +00:00
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