Samuel Pitoiset e8fb4b82e9 radv: fix emitting indirect descriptor sets in the DGC prepare shader ...

NIR_DEBUG=validate_ssa_dominance failed because dgc_cs_emit() weren't
actually in the if.

Fixes: 33a849e004 ("radv: emit indirect sets for indirect compute pipelines with DGC")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29782>

2024-06-20 06:33:51 +00:00

..

addrlib

amd: update addrlib

2024-06-08 00:11:17 -04:00

ci

ac/nir/tess: Fix per-patch output VRAM mapping.

2024-06-18 12:06:21 +00:00

common

ac/radv/radeon: move film grain init to common code.

2024-06-19 20:51:53 +00:00

compiler

aco: insert s_nop before discard early exit sendmsg(dealloc_vgpr)

2024-06-18 20:17:38 +00:00

drm-shim

amd: Use align64 instead of ALIGN for 64 bit value parameter

2024-01-03 22:02:17 +00:00

llvm

nir: remove nir_intrinsic_discard

2024-06-17 19:37:16 +00:00

registers

amd: add gfx12 register definitions

2024-05-11 22:14:05 -04:00

vpelib

amd/vpelib: Bypass de/regam on HLG

2024-05-07 20:43:02 +00:00

vulkan

radv: fix emitting indirect descriptor sets in the DGC prepare shader

2024-06-20 06:33:51 +00:00

meson.build

build/amd: add amd-use-llvm build option

2024-05-30 19:05:00 +00:00