Caio Oliveira
c418cb85f7
And change the gen_sort_xml.py script to default to the new format. Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
42 lines
2.3 KiB
XML
42 lines
2.3 KiB
XML
<?xml version='1.0' encoding='utf-8'?>
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<genxml name="RT" gen="30">
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<import name="gen200_rt.xml" />
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<struct name="BINDLESS_SHADER_RECORD" length="2">
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<field name="Offset To Local Arguments" dword="0" bits="2:0" type="uint" />
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<field name="Bindless Shader Dispatch Mode" dword="0" bits="4:4" type="uint">
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<value name="RT_SIMD16" value="0" />
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</field>
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<field name="Kernel Start Pointer" dword="0" bits="31:6" type="offset" />
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<field name="Registers Per Thread" dword="1" bits="31:28" type="uint" />
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</struct>
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<struct name="CALL_STACK_HANDLER" length="2">
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<field name="Offset To Local Arguments" dword="0" bits="2:0" type="uint" />
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<field name="Bindless Shader Dispatch Mode" dword="0" bits="4:4" type="uint">
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<value name="RT_SIMD16" value="0" />
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</field>
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<field name="Kernel Start Pointer" dword="0" bits="31:6" type="offset" />
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<field name="Registers Per Thread" dword="1" bits="30:27" type="uint" />
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</struct>
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<struct name="RT_DISPATCH_GLOBALS" length="21">
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<field name="Mem Base Address" dword="0" bits="63:0" type="address" />
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<field name="Call Stack Handler" dword="2" bits="63:0" type="CALL_STACK_HANDLER" />
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<field name="Async RT Stack Size" dword="4" bits="31:0" type="uint" />
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<field name="Num DSS RT Stacks" dword="5" bits="15:0" type="uint" />
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<field name="Max BVH Levels" dword="6" bits="2:0" type="uint" />
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<field name="Hit Group Stride" dword="6" bits="15:3" type="uint" />
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<field name="Miss Group Stride" dword="6" bits="28:16" type="uint" />
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<field name="Flags" dword="7" bits="0:0" type="uint">
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<value name="RT_DEPTH_TEST_LESS_EQUAL" value="1" />
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</field>
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<field name="Hit Group Table" dword="8" bits="63:0" type="address" />
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<field name="Miss Group Table" dword="10" bits="63:0" type="address" />
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<field name="SW Stack Size" dword="12" bits="31:0" type="uint" />
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<field name="Launch Width" dword="13" bits="31:0" type="uint" />
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<field name="Launch Height" dword="14" bits="31:0" type="uint" />
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<field name="Launch Depth" dword="15" bits="31:0" type="uint" />
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<field name="Callable Group Table" dword="16" bits="63:0" type="address" />
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<field name="Callable Group Stride" dword="18" bits="12:0" type="uint" />
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<field name="Resume Shader Table" dword="19" bits="63:0" type="address" />
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</struct>
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</genxml>
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