Timur Kristóf
930243bf36
There are some FS built-ins that can be per-vertex or per-primitive depending on whether a mesh shader is used: primitive ID (implicit in VS), layer and viewport. However, the HW requires per-primitive FS inputs to be ordered last. This causes bugs when the same unlinked FS is used together with VS/TES/GS and MS (with unlinked ESO or fast-linked GPL). To solve this problem, we reorder the FS inputs so that these potentially per-primitive inputs go after per-vertex inputs but before per-primitive inputs. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32220>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/*
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* Copyright © 2023 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_NIR_H
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#define RADV_NIR_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "amd_family.h"
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#include "nir.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct nir_shader nir_shader;
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struct radeon_info;
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struct radv_pipeline_layout;
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struct radv_shader_stage;
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struct radv_shader_info;
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struct radv_shader_args;
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struct radv_shader_layout;
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struct radv_device;
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struct radv_graphics_state_key;
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void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
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const struct radv_shader_stage *stage);
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void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage,
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const struct radv_graphics_state_key *gfx_state, uint32_t address32_hi);
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bool radv_nir_lower_hit_attrib_derefs(nir_shader *shader);
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bool radv_nir_lower_ray_payload_derefs(nir_shader *shader, uint32_t offset);
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bool radv_nir_lower_ray_queries(nir_shader *shader, struct radv_device *device);
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bool radv_nir_lower_vs_inputs(nir_shader *shader, const struct radv_shader_stage *vs_stage,
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const struct radv_graphics_state_key *gfx_state, const struct radeon_info *gpu_info);
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bool radv_nir_optimize_vs_inputs_to_const(nir_shader *shader, const struct radv_graphics_state_key *gfx_state);
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bool radv_nir_lower_primitive_shading_rate(nir_shader *nir, enum amd_gfx_level gfx_level);
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bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stage *fs_stage,
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const struct radv_graphics_state_key *gfx_state);
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bool radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_graphics_state_key *gfx_state,
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unsigned rast_prim);
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bool radv_nir_lower_intrinsics_early(nir_shader *nir, bool lower_view_index_to_zero);
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bool radv_nir_lower_view_index(nir_shader *nir);
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bool radv_nir_lower_viewport_to_zero(nir_shader *nir);
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bool radv_nir_export_multiview(nir_shader *nir);
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void radv_nir_lower_io_to_scalar_early(nir_shader *nir, nir_variable_mode mask);
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unsigned radv_map_io_driver_location(unsigned semantic);
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bool radv_recompute_fs_input_bases(nir_shader *nir);
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void radv_nir_lower_io(struct radv_device *device, nir_shader *nir);
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bool radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *stage);
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void radv_nir_lower_poly_line_smooth(nir_shader *nir, const struct radv_graphics_state_key *gfx_state);
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bool radv_nir_lower_cooperative_matrix(nir_shader *shader, unsigned wave_size);
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bool radv_nir_lower_draw_id_to_zero(nir_shader *shader);
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bool radv_nir_remap_color_attachment(nir_shader *shader, const struct radv_graphics_state_key *gfx_state);
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typedef struct radv_nir_opt_tid_function_options {
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bool use_masked_swizzle_amd : 1;
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bool use_dpp16_shift_amd : 1;
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bool use_shuffle_xor : 1;
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bool use_clustered_rotate : 1;
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/* The can be smaller than the api subgroup/ballot size
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* if some invocations are always inactive.
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*/
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uint8_t hw_subgroup_size;
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uint8_t hw_ballot_bit_size;
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uint8_t hw_ballot_num_comp;
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} radv_nir_opt_tid_function_options;
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bool radv_nir_opt_tid_function(nir_shader *shader, const radv_nir_opt_tid_function_options *options);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RADV_NIR_H */
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