Hans-Kristian Arntzen 5266bb0211 Fix DGC bug where indirect count > maxSequencesCount. ...

Need to explicitly clamp the indirect count against maxSequencesCount,
or we risk writing bogus commands into spill region.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23252>

2023-05-31 07:49:54 +00:00

..

addrlib

amd: update addrlib

2023-03-29 20:36:09 +00:00

ci

ci/amd: previously missed raven flake

2023-05-29 22:01:29 +02:00

common

ac, radeonsi: add and use ac_get_ps_iter_mask

2023-05-30 16:35:30 +00:00

compiler

aco: remove nir_intrinsic_load_barycentric_at_sample occurences

2023-05-31 07:25:46 +00:00

drm-shim

amd/drm-shim: add raven2

2023-05-22 20:14:22 +00:00

llvm

ac/llvm: use LLVM 0/1 constants from ac_llvm_context instead of LLVMConstInt

2023-05-26 23:27:59 -04:00

registers

ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT

2023-05-24 21:48:19 +00:00

vulkan

Fix DGC bug where indirect count > maxSequencesCount.

2023-05-31 07:49:54 +00:00

meson.build

meson: build radeonsi with aco

2023-05-15 02:01:10 +00:00