Files
mesa/src
Jason Ekstrand 493bfa54a5 i965/fs: Use the correct base_mrf for spilling pairs in SIMD8
Before, we were hard-coding the base_mrf based on dispatch width not number
of registers spilled at a time.  This caused us to emit instructions with a
base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
register.  This fixes the problem.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-10-02 16:38:25 -07:00
..
2014-04-14 00:06:53 -07:00
2014-09-27 15:20:49 +01:00