mesa/src at 46b346899d98e29943f8cd74c25bcb8d2f868a49 - mesa

Files

T

Topi Pohjolainen 46b346899d i965/gen6: Issue direct depth stall and flush after depth clear

instead of calling unconditionally brw_emit_mi_flush() which
does:

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                PIPE_CONTROL_RENDER_TARGET_FLUSH |
                                PIPE_CONTROL_CS_STALL);

   brw_emit_pipe_control_flush(brw,
                                PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
                                PIPE_CONTROL_CONST_CACHE_INVALIDATE);

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

2017-01-18 22:42:47 +02:00

amd

android: ac/debug: move sid_tables.h generation and IB decode to amd/common

2017-01-18 16:28:59 +00:00

compiler

utils: build sha1/disk cache only with Android/Autoconf

2017-01-18 20:09:01 +00:00

egl

egl/wayland: resolve quirky try_damage_buffer() implementation

2017-01-18 16:01:15 +00:00

gallium

radeonsi: determine in advance which VBOs should be added to the buffer list