Files
mesa/src/panfrost/compiler
Karol Herbst f2b7c4ce29 nir: rework and fix rotate lowering
No driver supports urol/uror on all bit sizes. Intel gen11+ only for 16
and 32 bit, Nvidia GV100+ only for 32 bit. Etnaviv can support it on 8,
16 and 32 bit.

Also turn the `lower` into a `has` option as only two drivers actually
support `uror` and `urol` at this momemt.

Fixes crashes with CL integer_rotate on iris and nouveau since we emit
urol for `rotate`.

v2: always lower 64 bit

Fixes: fe0965afa6 ("spirv: Don't use libclc for rotate")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by (Intel and nir): Ian Romanick <ian.d.romanick@intel.com>

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27090>
2024-01-22 10:27:44 +00:00
..
2023-05-29 21:06:12 +00:00
2023-08-14 21:22:52 +00:00

Bifrost compiler

Register file

Defined partially in software, partially in hardware.

Blend shaders

R0 - R3: input (color #0) R4 - R7: input (color #1) R8 - R15: general purpose R48: return address

Fragment

Anything live during BLEND must respect blend shader registers.

R0 - R3: preloaded (message #0) R4 - R7: preloaded (message #1) R57 - R63: preloaded (various)

R0 - R15: general purpose (full threads) R48 - R63: general purpose (full threads)

R32 - R47: general purpose (half threads, or v6)