I cut and pasted these comments from the Gen4 code during Ivybridge
enabling, and didn't understand what they meant at the time.
The data cache is NOT the same as the sampler cache on Ivybridge.
The sampler cache has L1 and L2 caches in addition to the L3 cache,
while data port messages to the "data cache" hit L3 directly.
This means that the sampler domain is technically wrong, but we stopped
caring about read/write domains quite a while ago. The kernel just
flushes all the caches at the end of each batchbuffer, and our render to
texture code flushes the sampler caches when necessary.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke
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