Dave Airlie f76f4be301 intel/compiler: move gen5 final pass to actually be final pass ...

This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fe ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>

2023-12-18 07:24:37 +00:00

..

blorp

blorp: Handle stencil buffer compression on blitter engine

2023-12-06 04:39:09 +00:00

ci

intel/ci: run only the relevant jobs when changing the ci expectations

2023-12-07 09:59:39 +00:00

common

intel: Sync xe_drm.h take 2 part 3

2023-12-06 17:35:23 +00:00

compiler

intel/compiler: move gen5 final pass to actually be final pass

2023-12-18 07:24:37 +00:00

dev

intel: Sync xe_drm.h take 2 part 3

2023-12-06 17:35:23 +00:00

ds

intel/ds: add trace of buffer markers

2023-11-29 01:16:22 +00:00

genxml

intel/genxml: Add BCS/VD0 aux table base address register

2023-12-14 00:53:15 +00:00

isl

isl: drop AUX-TT CCS alignment with INTEL_DEBUG=noccs

2023-12-13 17:40:38 +00:00

nullhw-layer

meson: support installation tags

2023-09-11 13:00:45 +00:00

perf

intel: Remove unused ALIGN macro

2023-12-07 02:30:53 +00:00

tools

intel/tools: fix compilation of intel_hang_viewer on 32 bits

2023-12-08 22:53:03 +00:00

vulkan

anv: Remove libdrm usage from Xe KMD backend

2023-12-15 20:40:49 +00:00

vulkan_hasvk

anv/hasvk/drirc: change anv_assume_full_subgroups to have subgroup size

2023-12-15 05:28:51 +00:00

meson.build

intel: Only build perf if drivers or tools are enabled

2023-08-31 21:53:19 +00:00