Anuj Phogat 3282c7be89 i965/icl: Fix L3 configurations ...

Use L3 configuration specified in h/w specification.

V2: Drop configs which do under allocation of l3 cache.
    Bump up the comment above table.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

2018-11-26 15:11:36 -08:00

..

gen_batch_decoder.c

intel/decoder: tools: Use engine for decoding batch instructions

2018-11-13 15:10:12 +00:00

gen_clflush.h

intel: Fix clflushing on modern (Baytrail+) Atom CPUs.

2017-07-10 15:55:26 -07:00

gen_debug.c

i965: add a debug option to disable oa config loading

2017-11-28 13:34:04 +00:00

gen_debug.h

i965: Disable shader cache with INTEL_DEBUG=shader_time

2018-08-01 23:30:49 -07:00

gen_decoder.c

intel/decoder: tools: Use engine for decoding batch instructions

2018-11-13 15:10:12 +00:00

gen_decoder.h

intel/decoder: tools: Use engine for decoding batch instructions

2018-11-13 15:10:12 +00:00

gen_defines.h

intel: add new common header gen_defines.h

2018-02-28 14:36:57 +02:00

gen_disasm.c

intel: Make the disassembler take a const pointer to the assembly.

2018-07-24 11:04:56 -07:00

gen_disasm.h

intel: Make the disassembler take a const pointer to the assembly.

2018-07-24 11:04:56 -07:00

gen_gem.h

intel: common: add missing stdint include

2018-08-04 09:39:01 +01:00

gen_l3_config.c

i965/icl: Fix L3 configurations

2018-11-26 15:11:36 -08:00

gen_l3_config.h

intel: Split gen_device_info out into libintel_dev

2018-03-05 09:47:37 -08:00

gen_sample_positions.h

intel: Switch the order of the 2x MSAA sample positions

2018-08-11 10:58:12 -05:00

gen_urb_config.c

intel: Use a URB start offset of 0 for disabled stages.

2018-11-03 23:25:57 -07:00

intel_log.c

intel: Add simple logging façade for Android (v2)

2017-10-17 11:08:26 -07:00

intel_log.h

intel: Add simple logging façade for Android (v2)

2017-10-17 11:08:26 -07:00

meson.build

anv: move canonical_address calculation into a separate function

2018-05-27 19:24:33 -07:00