Lionel Landwerlin 3b9466dd51 anv: fix transfer barriers flushes with compute queue ...

Transfer operation are implemented differently on the compute engine
and require a different kind of cache flush.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27233>

2024-01-26 20:47:18 +00:00

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blorp

intel: Add driver support for hardware generated local invocation IDs

2024-01-25 08:43:04 +00:00

ci

ci: bump kernel to 6.6.12, modularize i915, add Transparent Huge Pages

2024-01-23 00:41:48 +00:00

common

intel: Skip ioctls for querying device info when hardware is unsupported

2024-01-25 09:57:24 +00:00

compiler

intel/compiler: Enable lower_rotate_to_shuffle in subgroup lowering

2024-01-25 19:07:42 +00:00

dev

intel: Skip ioctls for querying device info when hardware is unsupported

2024-01-25 09:57:24 +00:00

ds

intel/ds: track predication of blorp operations

2024-01-26 13:39:01 +00:00

genxml

intel/genxml/xe2: Remove L3ALLOC

2024-01-18 14:16:17 +00:00

isl

isl,blorp,anv: introduce ISL_TILING_64_XE2 for Xe2+ platforms

2024-01-24 17:01:48 +01:00

nullhw-layer

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perf

intel: Remove unused ALIGN macro

2023-12-07 02:30:53 +00:00

tools

intel: Skip ioctls for querying device info when hardware is unsupported

2024-01-25 09:57:24 +00:00

vulkan

anv: fix transfer barriers flushes with compute queue

2024-01-26 20:47:18 +00:00

vulkan_hasvk

anv/hasvk: don't report error when intel_get_device_info_from_fd fails

2024-01-26 16:30:25 +00:00

meson.build

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