Qiang Yu 2b7e167bbd radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS ...

This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>

2022-06-27 02:38:21 +00:00

..

addrlib

amd: Initialize Gfx11Lib members in constructor.

2022-05-31 03:36:53 +00:00

ci

radv/ci: update vkd3d-proton results for AMD's Kabini

2022-06-24 05:32:53 +00:00

common

ac/nir: add no_input_lds_space param to hs output lower

2022-06-27 02:38:21 +00:00

compiler

aco: cleanup force-waitcnt output

2022-06-24 12:44:55 +00:00

drm-shim

Use proper types for meson objects

2022-04-18 13:03:08 +03:00

llvm

radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS

2022-06-27 02:38:21 +00:00

registers

amd/gfx11: add PixelWaitSync packet fields

2022-06-15 20:52:42 +00:00

vulkan

ac/nir: add no_input_lds_space param to hs output lower

2022-06-27 02:38:21 +00:00

.clang-format

radv: allow holes in inline push constants

2022-04-12 11:44:30 +00:00

meson.build

r300/r600: Add drm-shim support.

2022-02-02 00:59:08 +00:00