Danylo Piliaiev be46639974 freedreno/a7xx: Fix base_align for non-UBWC depth-stencil ...

A7XX appears to require alignment of 4096 for DS in both
UBWC and non-UBWC cases.

Fixes rendering with TU_DEBUG=noubwc

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27848>

2024-02-28 16:30:15 +00:00

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fd5_layout_test.c

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fd5_layout.c

freedreno/a5xx: Diff reduction in fd5_layout to fd6_layout.

2021-11-04 22:49:29 +00:00

fd6_format_table.c

freedreno/fdl: Support PIPE_FORMAT_R5G5B5A1_UNORM on a6xx

2023-09-27 19:07:22 +00:00

fd6_format_table.h

freedreno: c++-proofing

2023-03-13 17:31:22 +00:00

fd6_layout_test.c

freedreno/a6xx: Fix a bunch of 3D texture layout to match blob behavior.

2021-11-15 22:25:08 +00:00

fd6_layout.c

freedreno/a7xx: Fix base_align for non-UBWC depth-stencil

2024-02-28 16:30:15 +00:00

fd6_view.c

freedreno/fdl: Use A8_UNORM HW format for sampling

2023-09-27 19:07:22 +00:00

fd_layout_test.c

freedreno/cffdump: Handle the TILE_ALL flag in unit test generation.

2021-11-15 22:25:08 +00:00

fd_layout_test.h

freedreno/cffdump: Handle the TILE_ALL flag in unit test generation.

2021-11-15 22:25:08 +00:00

freedreno_layout.c

freedreno/fdl: Give the tiling mode a nice name in debug dumps.

2021-06-17 22:47:51 +00:00

freedreno_layout.h

freedreno/layout: Add layout metadata

2023-12-22 04:01:12 +00:00

meson.build

freedreno: decouple compiler and vulkan driver from gallium

2023-08-03 07:29:36 +00:00