1d8f46e00c
We're going to want to call it from a different file too. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
202 lines
6.8 KiB
C
202 lines
6.8 KiB
C
/*
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* Copyright © 2024 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_NIR_HELPERS_H
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#define AC_NIR_HELPERS_H
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#include "ac_hw_stage.h"
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#include "ac_shader_args.h"
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#include "ac_shader_util.h"
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#include "nir.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \
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do { \
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if ((store_val)->bit_size >= 32) { \
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const unsigned store_write_mask = (write_mask); \
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const unsigned store_const_offset = (const_offset); \
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func((b), (store_val), __VA_ARGS__); \
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} else { \
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u_foreach_bit(c, (write_mask)) { \
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const unsigned store_write_mask = 1; \
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const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \
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nir_def *store_component = nir_channel(b, (store_val), c); \
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func((b), store_component, __VA_ARGS__); \
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} \
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} \
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} while (0)
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#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \
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do { \
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const unsigned load_bit_size = MAX2(32, (bit_size)); \
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(load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \
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if ((bit_size) < load_bit_size) { \
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if ((hi_16bit)) { \
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(load) = nir_unpack_32_2x16_split_y(b, load); \
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} else { \
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(load) = nir_unpack_32_2x16_split_x(b, load); \
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} \
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} \
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} while (0)
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typedef struct
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{
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/* GS output stream index, 2 bit per component */
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uint8_t stream;
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/* Bitmask of components used: 4 bits per slot, 1 bit per component. */
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uint8_t components_mask : 4;
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/* Bitmask of components that are used as varying, 1 bit per component. */
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uint8_t as_varying_mask : 4;
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/* Bitmask of components that are used as sysval, 1 bit per component. */
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uint8_t as_sysval_mask : 4;
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} ac_nir_prerast_per_output_info;
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typedef struct
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{
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nir_def *outputs[VARYING_SLOT_MAX][4];
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nir_def *outputs_16bit_lo[16][4];
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nir_def *outputs_16bit_hi[16][4];
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nir_alu_type types[VARYING_SLOT_MAX][4];
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nir_alu_type types_16bit_lo[16][4];
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nir_alu_type types_16bit_hi[16][4];
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ac_nir_prerast_per_output_info infos[VARYING_SLOT_MAX];
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ac_nir_prerast_per_output_info infos_16bit_lo[16];
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ac_nir_prerast_per_output_info infos_16bit_hi[16];
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} ac_nir_prerast_out;
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/* Maps I/O semantics to the actual location used by the lowering pass. */
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typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
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/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
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struct nir_builder;
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typedef struct nir_builder nir_builder;
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struct nir_xfb_info;
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typedef struct nir_xfb_info nir_xfb_info;
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/* Executed by ac_nir_cull when the current primitive is accepted. */
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typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state);
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nir_def *
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ac_nir_unpack_value(nir_builder *b, nir_def *value, unsigned rshift, unsigned bitwidth);
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void
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ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value,
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unsigned component, unsigned writemask);
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void
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ac_nir_gather_prerast_store_output_info(nir_builder *b,
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nir_intrinsic_instr *intrin,
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ac_nir_prerast_out *out);
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void
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ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row);
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void
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ac_nir_export_position(nir_builder *b,
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enum amd_gfx_level gfx_level,
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uint32_t clip_cull_mask,
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bool no_param_export,
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bool force_vrs,
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bool done,
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uint64_t outputs_written,
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ac_nir_prerast_out *out,
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nir_def *row);
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void
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ac_nir_export_parameters(nir_builder *b,
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const uint8_t *param_offsets,
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uint64_t outputs_written,
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uint16_t outputs_written_16bit,
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ac_nir_prerast_out *out);
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void
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ac_nir_store_parameters_to_attr_ring(nir_builder *b,
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const uint8_t *param_offsets,
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const uint64_t outputs_written,
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const uint16_t outputs_written_16bit,
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ac_nir_prerast_out *out,
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nir_def *export_tid, nir_def *num_export_threads);
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nir_def *
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ac_nir_calc_io_off(nir_builder *b,
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nir_intrinsic_instr *intrin,
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nir_def *base_stride,
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unsigned component_stride,
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unsigned mapped_location);
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unsigned
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ac_nir_map_io_location(unsigned location,
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uint64_t mask,
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ac_nir_map_io_driver_location map_io);
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nir_def *
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ac_nir_cull_primitive(nir_builder *b,
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nir_def *initially_accepted,
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nir_def *pos[3][4],
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unsigned num_vertices,
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ac_nir_cull_accepted accept_func,
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void *state);
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void
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ac_nir_sleep(nir_builder *b, unsigned num_cycles);
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nir_def *
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ac_average_samples(nir_builder *b, nir_def **samples, unsigned num_samples);
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void
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ac_optimization_barrier_vgpr_array(const struct radeon_info *info, nir_builder *b,
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nir_def **array, unsigned num_elements,
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unsigned num_components);
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nir_def *
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ac_get_global_ids(nir_builder *b, unsigned num_components, unsigned bit_size);
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void
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ac_nir_emit_legacy_streamout(nir_builder *b, unsigned stream, nir_xfb_info *info, ac_nir_prerast_out *out);
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bool
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ac_nir_gs_shader_query(nir_builder *b,
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bool has_gen_prim_query,
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bool has_gs_invocations_query,
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bool has_gs_primitives_query,
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unsigned num_vertices_per_primitive,
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unsigned wave_size,
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nir_def *vertex_count[4],
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nir_def *primitive_count[4]);
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nir_def *
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ac_nir_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives,
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nir_def *vertex_indices[3], nir_def *is_null_prim,
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enum amd_gfx_level gfx_level);
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void
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ac_nir_clamp_vertex_color_outputs(nir_builder *b, ac_nir_prerast_out *out);
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void
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ac_nir_ngg_alloc_vertices_and_primitives(nir_builder *b,
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nir_def *num_vtx,
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nir_def *num_prim,
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bool fully_culled_workaround);
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void
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ac_nir_create_output_phis(nir_builder *b,
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const uint64_t outputs_written,
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const uint64_t outputs_written_16bit,
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ac_nir_prerast_out *out);
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC_NIR_HELPERS_H */
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