Samuel Pitoiset 164b1884c0 radv: bind our internal depth buffer when not provided by the app ...

When a subpass uses a VRS attachment without binding a depth/stencil
attachment (yes, this is allowed by the Vulkan spec), we have to bind
our internal depth buffer that contains the VRS data.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>

2021-04-14 09:31:13 +00:00

..

addrlib

amd/addrlib: expose HTILE address equations to drivers on GFX10+

2021-04-14 09:31:13 +00:00

ci

radv: change RADV_FORCE_FAMILY to use family name instead of LLVM processor name

2021-04-05 06:53:55 +00:00

common

ac/surface: store the HTILE pitch to the surface

2021-04-14 09:31:13 +00:00

compiler

aco/cssa: don't create parallelcopies for constants and exec

2021-04-13 18:40:57 +00:00

llvm

ac/llvm: implement 16-bit packed VS outputs and FS inputs

2021-04-13 21:10:43 -04:00

registers

amd: fix parsing the last dword of DMA_DATA packets

2021-04-02 12:05:00 +00:00

vulkan

radv: bind our internal depth buffer when not provided by the app

2021-04-14 09:31:13 +00:00

.clang-format

radv: Add clang-format for AMD code.

2021-04-10 03:31:32 +02:00

Android.addrlib.mk

android: amd/addrlib: define endianess to build

2021-03-27 01:54:49 +01:00

Android.common.mk

android: amd/registers: switch to new generated register definitions

2020-09-06 20:20:34 +02:00

Android.compiler.mk

android: aco/isel: Move context initialization code to a dedicated file

2020-09-14 21:26:53 +02:00

Android.mk

android: aco: add support for libmesa_aco

2019-09-28 15:56:34 +02:00

Makefile.sources

aco: add new reindex_ssa() pass

2021-04-13 18:40:57 +00:00

meson.build

aco: add framework for unit testing

2020-07-30 16:13:08 +00:00