mesa/src at 156bcca62c9f4e79e78929f72bc085757f36a65a - mesa

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Tom Stellard 156bcca62c r600g: Don't set the dest cache bits on surface sync for R600_CONTEXT_FLUSH_AND_INV

We are already emitting a EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet
when this flush flag is set, so flushing the dest caches with a
SURFACE_SYNC should not be necessary.

The motivation for this change is that emitting a SURFACE_SYNC packet with
the CB bits set was causing compute shaders to hang on Cayman.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

2013-05-02 09:00:37 -07:00

egl

egl/dri2: Fix min/max swap interval of configs

2013-04-24 08:05:13 +02:00

gallium

r600g: Don't set the dest cache bits on surface sync for R600_CONTEXT_FLUSH_AND_INV

2013-05-02 09:00:37 -07:00

gbm

gbm: Remember to init format on gbm_dri_bo_create.

2013-02-07 20:00:52 -05:00

getopt

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