Jordan Justen 0fc93928f1 isl: Don't enable HDC:L1 caches on DG2 ...

The MOCS entry used for this on Tigerlake doesn't exist on DG2.

Ref: aca31baafc ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14467>

2022-01-10 21:20:03 +00:00

..

blorp

intel/blorp: Modify get_fast_clear_rect for XeHP

2021-12-11 04:14:20 +00:00

ci

anv/ci: Test with deqp-vk on Tiger Lake

2022-01-07 13:33:32 +00:00

common

intel/l3: Make DG1 urb-size exception more generic

2021-12-11 00:09:50 +00:00

compiler

nir/algebraic: Separate has_dot_4x8 into has_sdot_4x8 and has_udot_4x8

2022-01-10 13:20:39 +02:00

dev

intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled.

2022-01-07 07:58:27 +00:00

ds

intel: move timestamp scaling helper to intel/perf

2021-11-22 11:52:46 +00:00

genxml

intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint

2021-12-30 11:40:33 +10:00

isl

isl: Don't enable HDC:L1 caches on DG2

2022-01-10 21:20:03 +00:00

nullhw-layer

intel/nullhw: fix build

2021-03-26 20:12:40 +00:00

perf

intel: move timestamp scaling helper to intel/perf

2021-11-22 11:52:46 +00:00

tools

intel/stub: Implement shell versions of DRM_I915_GEM_GET_TILING and DRM_I915_SEM_GET_TILING

2021-12-16 23:06:38 +00:00

vulkan

anv: Fixed maxFragmentCombinedOutputResources

2022-01-10 19:28:17 +00:00

Makefile.perf.am

intel: Rename GEN_PERF prefix to INTEL_PERF in build files

2021-04-20 20:06:34 +00:00

meson.build

pps: Intel pps driver

2021-05-18 14:28:48 +00:00