Alyssa Rosenzweig
09d31922de
Everything is SSA now.
sed -e 's/nir_ssa_def/nir_def/g' \
-e 's/nir_ssa_undef/nir_undef/g' \
-e 's/nir_ssa_scalar/nir_scalar/g' \
-e 's/nir_src_rewrite_ssa/nir_src_rewrite/g' \
-e 's/nir_gather_ssa_types/nir_gather_types/g' \
-i $(git grep -l nir | grep -v relnotes)
git mv src/compiler/nir/nir_gather_ssa_types.c \
src/compiler/nir/nir_gather_types.c
ninja -C build/ clang-format
cd src/compiler/nir && find *.c *.h -type f -exec clang-format -i \{} \;
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24585>
668 lines
31 KiB
C
668 lines
31 KiB
C
/*
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* Copyright © 2021 Google
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "radv_rt_common.h"
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#include "bvh/bvh.h"
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#include "radv_debug.h"
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#ifdef LLVM_AVAILABLE
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#include <llvm/Config/llvm-config.h>
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#endif
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static nir_def *build_node_to_addr(struct radv_device *device, nir_builder *b, nir_def *node, bool skip_type_and);
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bool
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radv_enable_rt(const struct radv_physical_device *pdevice, bool rt_pipelines)
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{
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if (pdevice->rad_info.gfx_level < GFX10_3 && !radv_emulate_rt(pdevice))
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return false;
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if (rt_pipelines && pdevice->use_llvm)
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return false;
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return true;
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}
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bool
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radv_emulate_rt(const struct radv_physical_device *pdevice)
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{
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return pdevice->instance->perftest_flags & RADV_PERFTEST_EMULATE_RT;
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}
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void
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nir_sort_hit_pair(nir_builder *b, nir_variable *var_distances, nir_variable *var_indices, uint32_t chan_1,
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uint32_t chan_2)
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{
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nir_def *ssa_distances = nir_load_var(b, var_distances);
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nir_def *ssa_indices = nir_load_var(b, var_indices);
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/* if (distances[chan_2] < distances[chan_1]) { */
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nir_push_if(b, nir_flt(b, nir_channel(b, ssa_distances, chan_2), nir_channel(b, ssa_distances, chan_1)));
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{
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/* swap(distances[chan_2], distances[chan_1]); */
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nir_def *new_distances[4] = {nir_undef(b, 1, 32), nir_undef(b, 1, 32), nir_undef(b, 1, 32), nir_undef(b, 1, 32)};
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nir_def *new_indices[4] = {nir_undef(b, 1, 32), nir_undef(b, 1, 32), nir_undef(b, 1, 32), nir_undef(b, 1, 32)};
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new_distances[chan_2] = nir_channel(b, ssa_distances, chan_1);
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new_distances[chan_1] = nir_channel(b, ssa_distances, chan_2);
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new_indices[chan_2] = nir_channel(b, ssa_indices, chan_1);
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new_indices[chan_1] = nir_channel(b, ssa_indices, chan_2);
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nir_store_var(b, var_distances, nir_vec(b, new_distances, 4), (1u << chan_1) | (1u << chan_2));
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nir_store_var(b, var_indices, nir_vec(b, new_indices, 4), (1u << chan_1) | (1u << chan_2));
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}
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/* } */
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nir_pop_if(b, NULL);
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}
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nir_def *
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intersect_ray_amd_software_box(struct radv_device *device, nir_builder *b, nir_def *bvh_node, nir_def *ray_tmax,
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nir_def *origin, nir_def *dir, nir_def *inv_dir)
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{
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const struct glsl_type *vec4_type = glsl_vector_type(GLSL_TYPE_FLOAT, 4);
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const struct glsl_type *uvec4_type = glsl_vector_type(GLSL_TYPE_UINT, 4);
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bool old_exact = b->exact;
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b->exact = true;
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nir_def *node_addr = build_node_to_addr(device, b, bvh_node, false);
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/* vec4 distances = vec4(INF, INF, INF, INF); */
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nir_variable *distances = nir_variable_create(b->shader, nir_var_shader_temp, vec4_type, "distances");
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nir_store_var(b, distances, nir_imm_vec4(b, INFINITY, INFINITY, INFINITY, INFINITY), 0xf);
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/* uvec4 child_indices = uvec4(0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff); */
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nir_variable *child_indices = nir_variable_create(b->shader, nir_var_shader_temp, uvec4_type, "child_indices");
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nir_store_var(b, child_indices, nir_imm_ivec4(b, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu), 0xf);
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/* Need to remove infinities here because otherwise we get nasty NaN propagation
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* if the direction has 0s in it. */
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/* inv_dir = clamp(inv_dir, -FLT_MAX, FLT_MAX); */
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inv_dir = nir_fclamp(b, inv_dir, nir_imm_float(b, -FLT_MAX), nir_imm_float(b, FLT_MAX));
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for (int i = 0; i < 4; i++) {
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const uint32_t child_offset = offsetof(struct radv_bvh_box32_node, children[i]);
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const uint32_t coord_offsets[2] = {
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offsetof(struct radv_bvh_box32_node, coords[i].min.x),
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offsetof(struct radv_bvh_box32_node, coords[i].max.x),
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};
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/* node->children[i] -> uint */
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nir_def *child_index = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, node_addr, child_offset), .align_mul = 64,
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.align_offset = child_offset % 64);
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/* node->coords[i][0], node->coords[i][1] -> vec3 */
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nir_def *node_coords[2] = {
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nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
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.align_offset = coord_offsets[0] % 64),
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nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
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.align_offset = coord_offsets[1] % 64),
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};
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/* If x of the aabb min is NaN, then this is an inactive aabb.
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* We don't need to care about any other components being NaN as that is UB.
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* https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap36.html#VkAabbPositionsKHR
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*/
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nir_def *min_x = nir_channel(b, node_coords[0], 0);
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nir_def *min_x_is_not_nan = nir_inot(b, nir_fneu(b, min_x, min_x)); /* NaN != NaN -> true */
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/* vec3 bound0 = (node->coords[i][0] - origin) * inv_dir; */
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nir_def *bound0 = nir_fmul(b, nir_fsub(b, node_coords[0], origin), inv_dir);
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/* vec3 bound1 = (node->coords[i][1] - origin) * inv_dir; */
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nir_def *bound1 = nir_fmul(b, nir_fsub(b, node_coords[1], origin), inv_dir);
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/* float tmin = max(max(min(bound0.x, bound1.x), min(bound0.y, bound1.y)), min(bound0.z,
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* bound1.z)); */
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nir_def *tmin = nir_fmax(b,
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nir_fmax(b, nir_fmin(b, nir_channel(b, bound0, 0), nir_channel(b, bound1, 0)),
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nir_fmin(b, nir_channel(b, bound0, 1), nir_channel(b, bound1, 1))),
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nir_fmin(b, nir_channel(b, bound0, 2), nir_channel(b, bound1, 2)));
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/* float tmax = min(min(max(bound0.x, bound1.x), max(bound0.y, bound1.y)), max(bound0.z,
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* bound1.z)); */
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nir_def *tmax = nir_fmin(b,
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nir_fmin(b, nir_fmax(b, nir_channel(b, bound0, 0), nir_channel(b, bound1, 0)),
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nir_fmax(b, nir_channel(b, bound0, 1), nir_channel(b, bound1, 1))),
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nir_fmax(b, nir_channel(b, bound0, 2), nir_channel(b, bound1, 2)));
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/* if (!isnan(node->coords[i][0].x) && tmax >= max(0.0f, tmin) && tmin < ray_tmax) { */
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nir_push_if(b, nir_iand(b, min_x_is_not_nan,
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nir_iand(b, nir_fge(b, tmax, nir_fmax(b, nir_imm_float(b, 0.0f), tmin)),
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nir_flt(b, tmin, ray_tmax))));
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{
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/* child_indices[i] = node->children[i]; */
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nir_def *new_child_indices[4] = {child_index, child_index, child_index, child_index};
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nir_store_var(b, child_indices, nir_vec(b, new_child_indices, 4), 1u << i);
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/* distances[i] = tmin; */
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nir_def *new_distances[4] = {tmin, tmin, tmin, tmin};
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nir_store_var(b, distances, nir_vec(b, new_distances, 4), 1u << i);
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}
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/* } */
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nir_pop_if(b, NULL);
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}
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/* Sort our distances with a sorting network. */
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nir_sort_hit_pair(b, distances, child_indices, 0, 1);
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nir_sort_hit_pair(b, distances, child_indices, 2, 3);
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nir_sort_hit_pair(b, distances, child_indices, 0, 2);
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nir_sort_hit_pair(b, distances, child_indices, 1, 3);
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nir_sort_hit_pair(b, distances, child_indices, 1, 2);
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b->exact = old_exact;
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return nir_load_var(b, child_indices);
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}
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nir_def *
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intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, nir_def *bvh_node, nir_def *ray_tmax,
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nir_def *origin, nir_def *dir, nir_def *inv_dir)
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{
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const struct glsl_type *vec4_type = glsl_vector_type(GLSL_TYPE_FLOAT, 4);
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bool old_exact = b->exact;
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b->exact = true;
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nir_def *node_addr = build_node_to_addr(device, b, bvh_node, false);
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const uint32_t coord_offsets[3] = {
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offsetof(struct radv_bvh_triangle_node, coords[0]),
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offsetof(struct radv_bvh_triangle_node, coords[1]),
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offsetof(struct radv_bvh_triangle_node, coords[2]),
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};
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/* node->coords[0], node->coords[1], node->coords[2] -> vec3 */
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nir_def *node_coords[3] = {
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nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
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.align_offset = coord_offsets[0] % 64),
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nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
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.align_offset = coord_offsets[1] % 64),
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nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[2]), .align_mul = 64,
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.align_offset = coord_offsets[2] % 64),
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};
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nir_variable *result = nir_variable_create(b->shader, nir_var_shader_temp, vec4_type, "result");
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nir_store_var(b, result, nir_imm_vec4(b, INFINITY, 1.0f, 0.0f, 0.0f), 0xf);
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/* Based on watertight Ray/Triangle intersection from
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* http://jcgt.org/published/0002/01/05/paper.pdf */
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/* Calculate the dimension where the ray direction is largest */
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nir_def *abs_dir = nir_fabs(b, dir);
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nir_def *abs_dirs[3] = {
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nir_channel(b, abs_dir, 0),
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nir_channel(b, abs_dir, 1),
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nir_channel(b, abs_dir, 2),
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};
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/* Find index of greatest value of abs_dir and put that as kz. */
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nir_def *kz = nir_bcsel(b, nir_fge(b, abs_dirs[0], abs_dirs[1]),
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nir_bcsel(b, nir_fge(b, abs_dirs[0], abs_dirs[2]), nir_imm_int(b, 0), nir_imm_int(b, 2)),
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nir_bcsel(b, nir_fge(b, abs_dirs[1], abs_dirs[2]), nir_imm_int(b, 1), nir_imm_int(b, 2)));
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nir_def *kx = nir_imod_imm(b, nir_iadd_imm(b, kz, 1), 3);
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nir_def *ky = nir_imod_imm(b, nir_iadd_imm(b, kx, 1), 3);
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nir_def *k_indices[3] = {kx, ky, kz};
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nir_def *k = nir_vec(b, k_indices, 3);
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/* Swap kx and ky dimensions to preserve winding order */
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unsigned swap_xy_swizzle[4] = {1, 0, 2, 3};
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k = nir_bcsel(b, nir_flt_imm(b, nir_vector_extract(b, dir, kz), 0.0f), nir_swizzle(b, k, swap_xy_swizzle, 3), k);
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kx = nir_channel(b, k, 0);
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ky = nir_channel(b, k, 1);
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kz = nir_channel(b, k, 2);
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/* Calculate shear constants */
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nir_def *sz = nir_frcp(b, nir_vector_extract(b, dir, kz));
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nir_def *sx = nir_fmul(b, nir_vector_extract(b, dir, kx), sz);
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nir_def *sy = nir_fmul(b, nir_vector_extract(b, dir, ky), sz);
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/* Calculate vertices relative to ray origin */
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nir_def *v_a = nir_fsub(b, node_coords[0], origin);
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nir_def *v_b = nir_fsub(b, node_coords[1], origin);
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nir_def *v_c = nir_fsub(b, node_coords[2], origin);
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/* Perform shear and scale */
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nir_def *ax = nir_fsub(b, nir_vector_extract(b, v_a, kx), nir_fmul(b, sx, nir_vector_extract(b, v_a, kz)));
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nir_def *ay = nir_fsub(b, nir_vector_extract(b, v_a, ky), nir_fmul(b, sy, nir_vector_extract(b, v_a, kz)));
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nir_def *bx = nir_fsub(b, nir_vector_extract(b, v_b, kx), nir_fmul(b, sx, nir_vector_extract(b, v_b, kz)));
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nir_def *by = nir_fsub(b, nir_vector_extract(b, v_b, ky), nir_fmul(b, sy, nir_vector_extract(b, v_b, kz)));
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nir_def *cx = nir_fsub(b, nir_vector_extract(b, v_c, kx), nir_fmul(b, sx, nir_vector_extract(b, v_c, kz)));
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nir_def *cy = nir_fsub(b, nir_vector_extract(b, v_c, ky), nir_fmul(b, sy, nir_vector_extract(b, v_c, kz)));
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nir_def *u = nir_fsub(b, nir_fmul(b, cx, by), nir_fmul(b, cy, bx));
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nir_def *v = nir_fsub(b, nir_fmul(b, ax, cy), nir_fmul(b, ay, cx));
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nir_def *w = nir_fsub(b, nir_fmul(b, bx, ay), nir_fmul(b, by, ax));
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/* Perform edge tests. */
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nir_def *cond_back =
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nir_ior(b, nir_ior(b, nir_flt_imm(b, u, 0.0f), nir_flt_imm(b, v, 0.0f)), nir_flt_imm(b, w, 0.0f));
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nir_def *cond_front =
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nir_ior(b, nir_ior(b, nir_fgt_imm(b, u, 0.0f), nir_fgt_imm(b, v, 0.0f)), nir_fgt_imm(b, w, 0.0f));
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nir_def *cond = nir_inot(b, nir_iand(b, cond_back, cond_front));
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/* If the ray is exactly on the edge where v is 0, consider it a miss.
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* This seems to correspond to what the hardware is doing.
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* Also, it avoids invoking hit shaders twice on a shared edge, which is
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* discouraged by the spec.
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*/
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cond = nir_iand(b, cond, nir_fneu(b, v, nir_imm_float(b, 0.0f)));
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nir_push_if(b, cond);
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{
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nir_def *det = nir_fadd(b, u, nir_fadd(b, v, w));
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nir_def *az = nir_fmul(b, sz, nir_vector_extract(b, v_a, kz));
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nir_def *bz = nir_fmul(b, sz, nir_vector_extract(b, v_b, kz));
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nir_def *cz = nir_fmul(b, sz, nir_vector_extract(b, v_c, kz));
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nir_def *t = nir_fadd(b, nir_fadd(b, nir_fmul(b, u, az), nir_fmul(b, v, bz)), nir_fmul(b, w, cz));
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nir_def *t_signed = nir_fmul(b, nir_fsign(b, det), t);
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nir_def *det_cond_front = nir_inot(b, nir_flt_imm(b, t_signed, 0.0f));
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nir_push_if(b, det_cond_front);
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{
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nir_def *indices[4] = {t, det, v, w};
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nir_store_var(b, result, nir_vec(b, indices, 4), 0xf);
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}
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nir_pop_if(b, NULL);
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}
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nir_pop_if(b, NULL);
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b->exact = old_exact;
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return nir_load_var(b, result);
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}
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nir_def *
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build_addr_to_node(nir_builder *b, nir_def *addr)
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{
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const uint64_t bvh_size = 1ull << 42;
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nir_def *node = nir_ushr_imm(b, addr, 3);
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return nir_iand_imm(b, node, (bvh_size - 1) << 3);
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}
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static nir_def *
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build_node_to_addr(struct radv_device *device, nir_builder *b, nir_def *node, bool skip_type_and)
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{
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nir_def *addr = skip_type_and ? node : nir_iand_imm(b, node, ~7ull);
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addr = nir_ishl_imm(b, addr, 3);
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/* Assumes everything is in the top half of address space, which is true in
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* GFX9+ for now. */
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return device->physical_device->rad_info.gfx_level >= GFX9 ? nir_ior_imm(b, addr, 0xffffull << 48) : addr;
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}
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nir_def *
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nir_build_vec3_mat_mult(nir_builder *b, nir_def *vec, nir_def *matrix[], bool translation)
|
|
{
|
|
nir_def *result_components[3] = {
|
|
nir_channel(b, matrix[0], 3),
|
|
nir_channel(b, matrix[1], 3),
|
|
nir_channel(b, matrix[2], 3),
|
|
};
|
|
for (unsigned i = 0; i < 3; ++i) {
|
|
for (unsigned j = 0; j < 3; ++j) {
|
|
nir_def *v = nir_fmul(b, nir_channels(b, vec, 1 << j), nir_channels(b, matrix[i], 1 << j));
|
|
result_components[i] = (translation || j) ? nir_fadd(b, result_components[i], v) : v;
|
|
}
|
|
}
|
|
return nir_vec(b, result_components, 3);
|
|
}
|
|
|
|
void
|
|
nir_build_wto_matrix_load(nir_builder *b, nir_def *instance_addr, nir_def **out)
|
|
{
|
|
unsigned offset = offsetof(struct radv_bvh_instance_node, wto_matrix);
|
|
for (unsigned i = 0; i < 3; ++i) {
|
|
out[i] = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16), .align_mul = 64,
|
|
.align_offset = offset + i * 16);
|
|
}
|
|
}
|
|
|
|
/* When a hit is opaque the any_hit shader is skipped for this hit and the hit
|
|
* is assumed to be an actual hit. */
|
|
static nir_def *
|
|
hit_is_opaque(nir_builder *b, nir_def *sbt_offset_and_flags, const struct radv_ray_flags *ray_flags,
|
|
nir_def *geometry_id_and_flags)
|
|
{
|
|
nir_def *opaque = nir_uge_imm(b, nir_ior(b, geometry_id_and_flags, sbt_offset_and_flags),
|
|
RADV_INSTANCE_FORCE_OPAQUE | RADV_INSTANCE_NO_FORCE_NOT_OPAQUE);
|
|
opaque = nir_bcsel(b, ray_flags->force_opaque, nir_imm_true(b), opaque);
|
|
opaque = nir_bcsel(b, ray_flags->force_not_opaque, nir_imm_false(b), opaque);
|
|
return opaque;
|
|
}
|
|
|
|
nir_def *
|
|
create_bvh_descriptor(nir_builder *b)
|
|
{
|
|
/* We create a BVH descriptor that covers the entire memory range. That way we can always
|
|
* use the same descriptor, which avoids divergence when different rays hit different
|
|
* instances at the cost of having to use 64-bit node ids. */
|
|
const uint64_t bvh_size = 1ull << 42;
|
|
return nir_imm_ivec4(b, 0, 1u << 31 /* Enable box sorting */, (bvh_size - 1) & 0xFFFFFFFFu,
|
|
((bvh_size - 1) >> 32) | (1u << 24 /* Return IJ for triangles */) | (1u << 31));
|
|
}
|
|
|
|
static void
|
|
insert_traversal_triangle_case(struct radv_device *device, nir_builder *b, const struct radv_ray_traversal_args *args,
|
|
const struct radv_ray_flags *ray_flags, nir_def *result, nir_def *bvh_node)
|
|
{
|
|
if (!args->triangle_cb)
|
|
return;
|
|
|
|
struct radv_triangle_intersection intersection;
|
|
intersection.t = nir_channel(b, result, 0);
|
|
nir_def *div = nir_channel(b, result, 1);
|
|
intersection.t = nir_fdiv(b, intersection.t, div);
|
|
|
|
nir_push_if(b, nir_flt(b, intersection.t, nir_load_deref(b, args->vars.tmax)));
|
|
{
|
|
intersection.frontface = nir_fgt_imm(b, div, 0);
|
|
nir_def *switch_ccw =
|
|
nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), RADV_INSTANCE_TRIANGLE_FLIP_FACING);
|
|
intersection.frontface = nir_ixor(b, intersection.frontface, switch_ccw);
|
|
|
|
nir_def *not_cull = ray_flags->no_skip_triangles;
|
|
nir_def *not_facing_cull =
|
|
nir_bcsel(b, intersection.frontface, ray_flags->no_cull_front, ray_flags->no_cull_back);
|
|
|
|
not_cull = nir_iand(b, not_cull,
|
|
nir_ior(b, not_facing_cull,
|
|
nir_test_mask(b, nir_load_deref(b, args->vars.sbt_offset_and_flags),
|
|
RADV_INSTANCE_TRIANGLE_FACING_CULL_DISABLE)));
|
|
|
|
nir_push_if(b, nir_iand(b,
|
|
|
|
nir_flt(b, args->tmin, intersection.t), not_cull));
|
|
{
|
|
intersection.base.node_addr = build_node_to_addr(device, b, bvh_node, false);
|
|
nir_def *triangle_info = nir_build_load_global(
|
|
b, 2, 32,
|
|
nir_iadd_imm(b, intersection.base.node_addr, offsetof(struct radv_bvh_triangle_node, triangle_id)));
|
|
intersection.base.primitive_id = nir_channel(b, triangle_info, 0);
|
|
intersection.base.geometry_id_and_flags = nir_channel(b, triangle_info, 1);
|
|
intersection.base.opaque = hit_is_opaque(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), ray_flags,
|
|
intersection.base.geometry_id_and_flags);
|
|
|
|
not_cull = nir_bcsel(b, intersection.base.opaque, ray_flags->no_cull_opaque, ray_flags->no_cull_no_opaque);
|
|
nir_push_if(b, not_cull);
|
|
{
|
|
nir_def *divs[2] = {div, div};
|
|
intersection.barycentrics = nir_fdiv(b, nir_channels(b, result, 0xc), nir_vec(b, divs, 2));
|
|
|
|
args->triangle_cb(b, &intersection, args, ray_flags);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
|
|
static void
|
|
insert_traversal_aabb_case(struct radv_device *device, nir_builder *b, const struct radv_ray_traversal_args *args,
|
|
const struct radv_ray_flags *ray_flags, nir_def *bvh_node)
|
|
{
|
|
if (!args->aabb_cb)
|
|
return;
|
|
|
|
struct radv_leaf_intersection intersection;
|
|
intersection.node_addr = build_node_to_addr(device, b, bvh_node, false);
|
|
nir_def *triangle_info = nir_build_load_global(
|
|
b, 2, 32, nir_iadd_imm(b, intersection.node_addr, offsetof(struct radv_bvh_aabb_node, primitive_id)));
|
|
intersection.primitive_id = nir_channel(b, triangle_info, 0);
|
|
intersection.geometry_id_and_flags = nir_channel(b, triangle_info, 1);
|
|
intersection.opaque = hit_is_opaque(b, nir_load_deref(b, args->vars.sbt_offset_and_flags), ray_flags,
|
|
intersection.geometry_id_and_flags);
|
|
|
|
nir_def *not_cull = nir_bcsel(b, intersection.opaque, ray_flags->no_cull_opaque, ray_flags->no_cull_no_opaque);
|
|
not_cull = nir_iand(b, not_cull, ray_flags->no_skip_aabbs);
|
|
nir_push_if(b, not_cull);
|
|
{
|
|
args->aabb_cb(b, &intersection, args);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
|
|
static nir_def *
|
|
fetch_parent_node(nir_builder *b, nir_def *bvh, nir_def *node)
|
|
{
|
|
nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, nir_udiv_imm(b, node, 8), 4), 4);
|
|
|
|
return nir_build_load_global(b, 1, 32, nir_isub(b, bvh, nir_u2u64(b, offset)), .align_mul = 4);
|
|
}
|
|
|
|
nir_def *
|
|
radv_build_ray_traversal(struct radv_device *device, nir_builder *b, const struct radv_ray_traversal_args *args)
|
|
{
|
|
nir_variable *incomplete = nir_local_variable_create(b->impl, glsl_bool_type(), "incomplete");
|
|
nir_store_var(b, incomplete, nir_imm_true(b), 0x1);
|
|
|
|
nir_def *desc = create_bvh_descriptor(b);
|
|
nir_def *vec3ones = nir_imm_vec3(b, 1.0, 1.0, 1.0);
|
|
|
|
struct radv_ray_flags ray_flags = {
|
|
.force_opaque = nir_test_mask(b, args->flags, SpvRayFlagsOpaqueKHRMask),
|
|
.force_not_opaque = nir_test_mask(b, args->flags, SpvRayFlagsNoOpaqueKHRMask),
|
|
.terminate_on_first_hit = nir_test_mask(b, args->flags, SpvRayFlagsTerminateOnFirstHitKHRMask),
|
|
.no_cull_front = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullFrontFacingTrianglesKHRMask), 0),
|
|
.no_cull_back = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullBackFacingTrianglesKHRMask), 0),
|
|
.no_cull_opaque = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullOpaqueKHRMask), 0),
|
|
.no_cull_no_opaque = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsCullNoOpaqueKHRMask), 0),
|
|
.no_skip_triangles = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsSkipTrianglesKHRMask), 0),
|
|
.no_skip_aabbs = nir_ieq_imm(b, nir_iand_imm(b, args->flags, SpvRayFlagsSkipAABBsKHRMask), 0),
|
|
};
|
|
nir_push_loop(b);
|
|
{
|
|
nir_push_if(b, nir_ieq_imm(b, nir_load_deref(b, args->vars.current_node), RADV_BVH_INVALID_NODE));
|
|
{
|
|
/* Early exit if we never overflowed the stack, to avoid having to backtrack to
|
|
* the root for no reason. */
|
|
nir_push_if(b, nir_ilt_imm(b, nir_load_deref(b, args->vars.stack), args->stack_base + args->stack_stride));
|
|
{
|
|
nir_store_var(b, incomplete, nir_imm_false(b), 0x1);
|
|
nir_jump(b, nir_jump_break);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
|
|
nir_def *stack_instance_exit =
|
|
nir_ige(b, nir_load_deref(b, args->vars.top_stack), nir_load_deref(b, args->vars.stack));
|
|
nir_def *root_instance_exit =
|
|
nir_ieq(b, nir_load_deref(b, args->vars.previous_node), nir_load_deref(b, args->vars.instance_bottom_node));
|
|
nir_if *instance_exit = nir_push_if(b, nir_ior(b, stack_instance_exit, root_instance_exit));
|
|
instance_exit->control = nir_selection_control_dont_flatten;
|
|
{
|
|
nir_store_deref(b, args->vars.top_stack, nir_imm_int(b, -1), 1);
|
|
nir_store_deref(b, args->vars.previous_node, nir_load_deref(b, args->vars.instance_top_node), 1);
|
|
nir_store_deref(b, args->vars.instance_bottom_node, nir_imm_int(b, RADV_BVH_NO_INSTANCE_ROOT), 1);
|
|
|
|
nir_store_deref(b, args->vars.bvh_base, args->root_bvh_base, 1);
|
|
nir_store_deref(b, args->vars.origin, args->origin, 7);
|
|
nir_store_deref(b, args->vars.dir, args->dir, 7);
|
|
nir_store_deref(b, args->vars.inv_dir, nir_fdiv(b, vec3ones, args->dir), 7);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
|
|
nir_push_if(
|
|
b, nir_ige(b, nir_load_deref(b, args->vars.stack_low_watermark), nir_load_deref(b, args->vars.stack)));
|
|
{
|
|
nir_def *prev = nir_load_deref(b, args->vars.previous_node);
|
|
nir_def *bvh_addr = build_node_to_addr(device, b, nir_load_deref(b, args->vars.bvh_base), true);
|
|
|
|
nir_def *parent = fetch_parent_node(b, bvh_addr, prev);
|
|
nir_push_if(b, nir_ieq_imm(b, parent, RADV_BVH_INVALID_NODE));
|
|
{
|
|
nir_store_var(b, incomplete, nir_imm_false(b), 0x1);
|
|
nir_jump(b, nir_jump_break);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
nir_store_deref(b, args->vars.current_node, parent, 0x1);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
nir_store_deref(b, args->vars.stack,
|
|
nir_iadd_imm(b, nir_load_deref(b, args->vars.stack), -args->stack_stride), 1);
|
|
|
|
nir_def *stack_ptr =
|
|
nir_umod_imm(b, nir_load_deref(b, args->vars.stack), args->stack_stride * args->stack_entries);
|
|
nir_def *bvh_node = args->stack_load_cb(b, stack_ptr, args);
|
|
nir_store_deref(b, args->vars.current_node, bvh_node, 0x1);
|
|
nir_store_deref(b, args->vars.previous_node, nir_imm_int(b, RADV_BVH_INVALID_NODE), 0x1);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
nir_store_deref(b, args->vars.previous_node, nir_imm_int(b, RADV_BVH_INVALID_NODE), 0x1);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
|
|
nir_def *bvh_node = nir_load_deref(b, args->vars.current_node);
|
|
|
|
nir_def *prev_node = nir_load_deref(b, args->vars.previous_node);
|
|
nir_store_deref(b, args->vars.previous_node, bvh_node, 0x1);
|
|
nir_store_deref(b, args->vars.current_node, nir_imm_int(b, RADV_BVH_INVALID_NODE), 0x1);
|
|
|
|
nir_def *global_bvh_node = nir_iadd(b, nir_load_deref(b, args->vars.bvh_base), nir_u2u64(b, bvh_node));
|
|
|
|
nir_def *intrinsic_result = NULL;
|
|
if (!radv_emulate_rt(device->physical_device)) {
|
|
intrinsic_result =
|
|
nir_bvh64_intersect_ray_amd(b, 32, desc, nir_unpack_64_2x32(b, global_bvh_node),
|
|
nir_load_deref(b, args->vars.tmax), nir_load_deref(b, args->vars.origin),
|
|
nir_load_deref(b, args->vars.dir), nir_load_deref(b, args->vars.inv_dir));
|
|
}
|
|
|
|
nir_def *node_type = nir_iand_imm(b, bvh_node, 7);
|
|
nir_push_if(b, nir_uge_imm(b, node_type, radv_bvh_node_box16));
|
|
{
|
|
nir_push_if(b, nir_uge_imm(b, node_type, radv_bvh_node_instance));
|
|
{
|
|
nir_push_if(b, nir_ieq_imm(b, node_type, radv_bvh_node_aabb));
|
|
{
|
|
insert_traversal_aabb_case(device, b, args, &ray_flags, global_bvh_node);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
/* instance */
|
|
nir_def *instance_node_addr = build_node_to_addr(device, b, global_bvh_node, false);
|
|
nir_store_deref(b, args->vars.instance_addr, instance_node_addr, 1);
|
|
|
|
nir_def *instance_data =
|
|
nir_build_load_global(b, 4, 32, instance_node_addr, .align_mul = 64, .align_offset = 0);
|
|
|
|
nir_def *wto_matrix[3];
|
|
nir_build_wto_matrix_load(b, instance_node_addr, wto_matrix);
|
|
|
|
nir_store_deref(b, args->vars.sbt_offset_and_flags, nir_channel(b, instance_data, 3), 1);
|
|
|
|
nir_def *instance_and_mask = nir_channel(b, instance_data, 2);
|
|
nir_push_if(b, nir_ult(b, nir_iand(b, instance_and_mask, args->cull_mask), nir_imm_int(b, 1 << 24)));
|
|
{
|
|
nir_jump(b, nir_jump_continue);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
|
|
nir_store_deref(b, args->vars.top_stack, nir_load_deref(b, args->vars.stack), 1);
|
|
nir_store_deref(b, args->vars.bvh_base, nir_pack_64_2x32(b, nir_trim_vector(b, instance_data, 2)), 1);
|
|
|
|
/* Push the instance root node onto the stack */
|
|
nir_store_deref(b, args->vars.current_node, nir_imm_int(b, RADV_BVH_ROOT_NODE), 0x1);
|
|
nir_store_deref(b, args->vars.instance_bottom_node, nir_imm_int(b, RADV_BVH_ROOT_NODE), 1);
|
|
nir_store_deref(b, args->vars.instance_top_node, bvh_node, 1);
|
|
|
|
/* Transform the ray into object space */
|
|
nir_store_deref(b, args->vars.origin, nir_build_vec3_mat_mult(b, args->origin, wto_matrix, true), 7);
|
|
nir_store_deref(b, args->vars.dir, nir_build_vec3_mat_mult(b, args->dir, wto_matrix, false), 7);
|
|
nir_store_deref(b, args->vars.inv_dir, nir_fdiv(b, vec3ones, nir_load_deref(b, args->vars.dir)), 7);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
nir_def *result = intrinsic_result;
|
|
if (!result) {
|
|
/* If we didn't run the intrinsic cause the hardware didn't support it,
|
|
* emulate ray/box intersection here */
|
|
result = intersect_ray_amd_software_box(
|
|
device, b, global_bvh_node, nir_load_deref(b, args->vars.tmax), nir_load_deref(b, args->vars.origin),
|
|
nir_load_deref(b, args->vars.dir), nir_load_deref(b, args->vars.inv_dir));
|
|
}
|
|
|
|
/* box */
|
|
nir_push_if(b, nir_ieq_imm(b, prev_node, RADV_BVH_INVALID_NODE));
|
|
{
|
|
nir_def *new_nodes[4];
|
|
for (unsigned i = 0; i < 4; ++i)
|
|
new_nodes[i] = nir_channel(b, result, i);
|
|
|
|
for (unsigned i = 1; i < 4; ++i)
|
|
nir_push_if(b, nir_ine_imm(b, new_nodes[i], RADV_BVH_INVALID_NODE));
|
|
|
|
for (unsigned i = 4; i-- > 1;) {
|
|
nir_def *stack = nir_load_deref(b, args->vars.stack);
|
|
nir_def *stack_ptr = nir_umod_imm(b, stack, args->stack_entries * args->stack_stride);
|
|
args->stack_store_cb(b, stack_ptr, new_nodes[i], args);
|
|
nir_store_deref(b, args->vars.stack, nir_iadd_imm(b, stack, args->stack_stride), 1);
|
|
|
|
if (i == 1) {
|
|
nir_def *new_watermark =
|
|
nir_iadd_imm(b, nir_load_deref(b, args->vars.stack), -args->stack_entries * args->stack_stride);
|
|
new_watermark = nir_imax(b, nir_load_deref(b, args->vars.stack_low_watermark), new_watermark);
|
|
nir_store_deref(b, args->vars.stack_low_watermark, new_watermark, 0x1);
|
|
}
|
|
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_store_deref(b, args->vars.current_node, new_nodes[0], 0x1);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
nir_def *next = nir_imm_int(b, RADV_BVH_INVALID_NODE);
|
|
for (unsigned i = 0; i < 3; ++i) {
|
|
next = nir_bcsel(b, nir_ieq(b, prev_node, nir_channel(b, result, i)), nir_channel(b, result, i + 1),
|
|
next);
|
|
}
|
|
nir_store_deref(b, args->vars.current_node, next, 0x1);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_push_else(b, NULL);
|
|
{
|
|
nir_def *result = intrinsic_result;
|
|
if (!result) {
|
|
/* If we didn't run the intrinsic cause the hardware didn't support it,
|
|
* emulate ray/tri intersection here */
|
|
result = intersect_ray_amd_software_tri(
|
|
device, b, global_bvh_node, nir_load_deref(b, args->vars.tmax), nir_load_deref(b, args->vars.origin),
|
|
nir_load_deref(b, args->vars.dir), nir_load_deref(b, args->vars.inv_dir));
|
|
}
|
|
insert_traversal_triangle_case(device, b, args, &ray_flags, result, global_bvh_node);
|
|
}
|
|
nir_pop_if(b, NULL);
|
|
}
|
|
nir_pop_loop(b, NULL);
|
|
|
|
return nir_load_var(b, incomplete);
|
|
}
|