Daniel Schürmann f3be7ce01b nir/from_ssa: only consider divergence if requested ...

This pass used to unconditionally use divergence information
which forced the caller to either call divergence_analysis or
ensure that the divergence is properly reset.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33009>

2025-01-23 01:31:23 +00:00

..

lib

…

meson.build

build: pass licensing information in SPDX form

2024-06-29 12:42:49 -07:00

nv50_ir_bb.cpp

…

nv50_ir_build_util.cpp

…

nv50_ir_build_util.h

…

nv50_ir_driver.h

…

nv50_ir_emit_gk110.cpp

…

nv50_ir_emit_gm107.cpp

…

nv50_ir_emit_gv100.cpp

…

nv50_ir_emit_gv100.h

…

nv50_ir_emit_nv50.cpp

…

nv50_ir_emit_nvc0.cpp

…

nv50_ir_from_nir.cpp

nir/from_ssa: only consider divergence if requested

2025-01-23 01:31:23 +00:00

nv50_ir_graph.cpp

…

nv50_ir_graph.h

…

nv50_ir_inlines.h

…

nv50_ir_lowering_gm107.cpp

…

nv50_ir_lowering_gm107.h

…

nv50_ir_lowering_gv100.cpp

…

nv50_ir_lowering_gv100.h

…

nv50_ir_lowering_helper.cpp

…

nv50_ir_lowering_helper.h

…

nv50_ir_lowering_nv50.cpp

…

nv50_ir_lowering_nvc0.cpp

…

nv50_ir_lowering_nvc0.h

…

nv50_ir_peephole.cpp

nv/codegen: Limit MemoryOpt to input/output/const

2024-08-21 02:59:44 +00:00

nv50_ir_print.cpp

…

nv50_ir_ra.cpp

…

nv50_ir_sched_gm107.h

…

nv50_ir_serialize.cpp

…

nv50_ir_ssa.cpp

…

nv50_ir_target_gm107.cpp

…

nv50_ir_target_gm107.h

…

nv50_ir_target_gv100.cpp

…

nv50_ir_target_gv100.h

…

nv50_ir_target_nv50.cpp

…

nv50_ir_target_nv50.h

…

nv50_ir_target_nvc0.cpp

…

nv50_ir_target_nvc0.h

…

nv50_ir_target.cpp

…

nv50_ir_target.h

…

nv50_ir_util.cpp

…

nv50_ir_util.h

…

nv50_ir.cpp

…

nv50_ir.h

…