Alyssa Rosenzweig 03c18f7efc nir/lower_mediump_io: Don't remap base unless needed ...

Otherwise drivers that don't use 16-bit slots for varyings will get
confused and have their driver_locations scribbled over. This has caused
multiple problems for both Panfrost and Asahi this week. Given the only
other user of the pass for varyings is radeonsi, which needs both
together, I think this is the least controversial fix.

Fixes: fb29cef8dd ("nir: add many passes that lower and optimize 16-bit input/outputs and samplers")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11732>

2021-08-10 20:55:33 +00:00

..

glsl

glsl: evaluate switch expression once

2021-08-10 09:04:17 +00:00

nir

nir/lower_mediump_io: Don't remap base unless needed

2021-08-10 20:55:33 +00:00

spirv

vtn: add support for atomic flag test/set/clear

2021-08-06 11:11:04 +10:00

builtin_type_macros.h

compiler/types: Add 64-bit image types

2020-11-09 17:17:39 +00:00

glsl_types.cpp

glsl: add missing support for explicit components in interface blocks

2021-05-13 08:07:53 +00:00

glsl_types.h

glsl: add missing support for explicit components in interface blocks

2021-05-13 08:07:53 +00:00

meson.build

spirv: add some tests for volatile/available/visible

2020-09-01 17:15:22 +00:00

nir_types.cpp

nir: Add a size_align helper function for aligning elements to 16 bytes.

2020-11-16 13:54:22 -08:00

nir_types.h

nir: Add a size_align helper function for aligning elements to 16 bytes.

2020-11-16 13:54:22 -08:00

shader_enums.c

tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling

2021-08-05 16:35:41 +00:00

shader_enums.h

tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling

2021-08-05 16:35:41 +00:00

shader_info.h

mesa: move gl_program::is_arb_asm to shader_info

2021-07-28 08:49:30 +00:00