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Author SHA1 Message Date
Lionel Landwerlin 4ab38112f3 anv: fixup assertions on lowered storage formats 
With VK_FORMAT_B10G11R11_UFLOAT_PACK32 in particular, we're seeing
applications create image views with swizzle = R,G,B,0

But since the format has no alpha channel, the swizzle value for it
does not matter for the equivalence we're trying to verify.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a9edc268b9 ("anv: validate image view lowered storage formats for storage")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18081>
 2022-08-23 08:29:51 +00:00
sjfricke 861167f41d isl: fix bug where sb.MOCS is not being set 
Currently the sb.MOCS is being reset to zero after struct init.

Signed-off-by: sjfricke <spencerfricke@gmail.com>
Fixes: c27fcb1d3b ("isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17985>
 2022-08-12 12:35:54 +00:00
Sagar Ghuge d4b2b769d1 intel/isl: Setting L1 caching policy to Write-back mode 
For a RW L1 cache, both reads and writes are cached in the L1, at high
priority (MRU position). For a RO L1 cache, reads are cached at higher
priority and writes bypass the cache.

v1: (Ken)
- Set caching policy for buffer surfaces too

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16905>
 2022-08-05 10:43:50 +03:00
Lionel Landwerlin ab4beaf3fb isl: add new helper for format component compatibility 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17329>
 2022-07-11 14:57:26 +00:00
Jason Ekstrand bc5e77a9f2 isl: Use util_sign_extend 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214>
 2022-07-06 11:23:18 +00:00
Marcin Ślusarz f4386b81e6 intel: fix typos found by codespell 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
 2022-06-27 10:20:55 +00:00
Erik Faye-Lund df4fe7c4a2 intel/isl: remove needless c99_compat.h includes 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
 2022-06-02 13:09:16 +00:00
Kenneth Graunke f052e00a58 isl: Add an isl_format_supports_typed_atomics() helper. 
v2: Add a fields in isl_format with per gen support (Lionel)

v3: Fixup R32_FLOAT from 80 to 90
    Fixup R32_[SU]INT from 80 to 70 (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14712>
 2022-06-01 10:05:19 +00:00
Jason Ekstrand faa51a10ed isl: Add some asserts about multisampled surfaces 
This isn't really necessary because the API doesn't allow MSAA and
mipmapping at the same time but people forget that pretty often so it's
good to have it as documentation if nothing else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
 2022-05-31 13:42:28 +00:00
Jason Ekstrand a19ed1f46a intel/isl: Add isl_view::min_lod_clamp for IVB+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14129>
 2022-05-31 13:42:28 +00:00
Nanley Chery b023f18bad isl,iris: Add DG2 CCS modifier support for XeHP 
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Nanley Chery a53abeb7fb intel/isl: Add a score for I915_FORMAT_MOD_4_TILED 
Enables the modifier in anv.

Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Anuj Phogat ac441d0953 isl,iris: Add I915_FORMAT_MOD_4_TILED support for XeHP 
This patch adds Tile 4 modifier support to Mesa and allows Mesa to
use Tile 4 on gen12-hp with GBM.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
 2022-04-28 20:02:14 +00:00
Tapani Pälli d3ef3657b2 isl: disable mcs (and mcs+ccs) for color msaa on DG2 
Fixes lots of various test failures in:
   dEQP-VK.pipeline.multisample.min_sample_shading_disabled.*
   dEQP-GLES3.functional*multisample.*
   KHR-GL*sample_variables.*

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13991>
 2022-04-28 05:31:52 +00:00
Jason Ekstrand 257a20f40d intel/isl: Add a helper for swizzling color values 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15624>
 2022-04-04 21:42:23 +00:00
Mike Blumenkrantz 65ec846f77 intel/isl: fix 2d view of 3d textures 
according to KHR_gl_texture_3D_image:

    If <target> is EGL_GL_TEXTURE_3D_KHR, <buffer> must be the name of a
    complete, nonzero, GL_TEXTURE_3D (or equivalent in GL extensions) target
    texture object, cast
    into the type EGLClientBuffer.  <attr_list> should specify the mipmap
    level (EGL_GL_TEXTURE_LEVEL_KHR) and z-offset (EGL_GL_TEXTURE_ZOFFSET_KHR)
    which will be used as the EGLImage source; the specified mipmap level must
    be part of <buffer>, and the specified z-offset must be smaller than the
    depth of the specified mipmap level.

thus a 2d view of a 3d surface is not only legal, it's part of the spec and
must be supported when available

cc: mesa-stable

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15584>
 2022-03-29 21:44:51 +00:00
Kenneth Graunke 49dd707ca2 intel: Add INTEL_DEBUG=noccs alias for INTEL_DEBUG=norbc 
When CCS compression first came out on Skylake, we referred to it as
"renderbuffer compression", or RBC for short.  However, that name has
long since fallen out of favor, and we refer to it as CCS nearly
everywhere.

This patch renames DEBUG_NO_RBC to DEBUG_NO_CCS inside the codebase
for clarity, and adds INTEL_DEBUG=noccs.  The legacy INTEL_DEBUG=norbc
name continues to work, because it's one line of code and having both
names makes our lives easier in the interim.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15447>
 2022-03-22 06:23:10 +00:00
Nanley Chery 85a7fb1e19 intel/isl: Add format assertions for surfaces using CCS 
This caught some invalid CCS surface states created by iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>
 2022-02-10 04:47:14 +00:00
Lionel Landwerlin 3ab7f4471c isl: disable CPB surface compression 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin dff08cbf8e isl: add support for coarse pixel control surfaces 
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.

v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)

v3: Drop unused macro (Nanley)
    s/isl_to_gen/isl_encode/ (Nanley)
    Remove pitch alignment 128B constraint already covered by tiling (Nanley)
    Move some asserts together (Nanley)

v4: Disable miptail for now (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Nanley Chery f724f95542 intel/isl: Add more PRM text for HiZ/STC requirement 
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery bc9ce9705c intel/isl: Fix depth buffer TiledSurface programming 
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.

Fixes: b77d694223 ("intel/isl: Allow HiZ with Tile4/64 surfaces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery 146213d0ee intel/isl: Simplify Z-buffer tiling config during emit 
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
 2022-02-02 16:25:10 +00:00
Nanley Chery 7f46e569e5 intel/isl: Support the XeHP media compression format 
The format on this platform is slightly different from the one used on
TGL. Also it's part of the surface state instead of an aux-map.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00
Nanley Chery fde43bb194 intel: Rename a RenderCompressionFormat field 
The name of the bit field is CompressionFormat. The format subsections
of the field specify the alternate names of RenderCompressionFormat or
MediaCompressionFormat depending on the compression type.

We're going to start programming this field for media compression, so
we'd like to use either the bit field name or a new
MediaCompressionFormat field. Either option seems fine, so we go with
the first.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00
Nanley Chery cc973de5f6 intel/isl: Support YUV pipe-to-isl format mapping 
This will help to configure surfaces for media compression.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
 2022-01-28 00:30:55 +00:00
Nanley Chery 749b82238b isl: Enable compression with multisampled Tile64 
We haven't tested the single-sampled case, so this doesn't enable any
more uses of standalone CCS. This does however, allow multisampled
surfaces with MCS or HIZ to get upgraded to MCS_CCS and HIZ_CCS,
respectively.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
 2022-01-27 22:38:01 +00:00
Jordan Justen 792e294572 isl: Enable compression with Tile4 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
 2022-01-27 22:38:01 +00:00
Kenneth Graunke 4d4f57b15c isl: Add isl_dev->mocs.blitter_{src,dst} fields 
These will be used for XY_BLOCK_COPY_BLT on XeHP.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>
 2022-01-24 23:27:25 +00:00
Nanley Chery f1f65e5bcf intel/isl: Allow creating MCS in Tile4 memory 
This enables MCS support on XeHP, now that MCS can be created with a
tiling supported by that platform.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
 2022-01-21 20:38:05 +00:00
Nanley Chery 58a843ab14 Revert "intel/isl: Don't reconfigure aux surfaces for MCS" 
This reverts commit 2f0fbe06e6.

We don't handle the reconfiguration of existing HiZ surfaces, nor do we
do so for CCS surfaces. This code path is unused, so we remove it.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
 2022-01-21 20:38:05 +00:00
Nanley Chery 531b1b7511 intel/isl: Strengthen MCS SINT format restriction 
The gfx7 MCS restriction for SINT formats actually applies to
multisampling in general. Place the stronger restriction in the format
support check and assert this in isl_surf_get_mcs_surf.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
 2022-01-21 20:38:05 +00:00
Nanley Chery bf9466e285 intel/isl: Don't check pitch in isl_surf_get_mcs_surf 
The pitch check for 16x multisampled surfaces should already be covered
by the pitch_in_range check in isl_calc_row_pitch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
 2022-01-21 20:38:05 +00:00
Lionel Landwerlin 246e2c74d3 isl: add helpers to printout ops 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996>
 2022-01-14 20:17:44 +00:00
Nanley Chery 1619279219 intel/isl: Return false more in isl_surf_get_hiz_surf 
Follow the CCS and MCS functions by returning false for unsupported
cases. This reduces the burden on the caller.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Nanley Chery b77d694223 intel/isl: Allow HiZ with Tile4/64 surfaces 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Nanley Chery 50967402cc intel/isl: Require Y-tiling for depth on gfx4-5 
This enables isl_surf_get_hiz_surf to be simplified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Nanley Chery 267689a269 intel/isl: Use a new HiZ format on XeHP+ 
The new HiZ compresses twice as many rows of the depth surface compared
to TGL (Bspec 47009). Also, its tiling needs to be specified in
3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Nanley Chery 7d0e847856 intel/isl: Update comment for the XeHP HiZ block 
An 8x4 HiZ block doesn't fit in with the new formulas for sizing HiZ on
XeHP. Update a comment which assumed this block size on SKL+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Nanley Chery e0ddeec209 intel/isl: Rework HiZ image align calculations 
* Check the format's compression type instead of the format directly to
  prepare for a new HiZ format on XeHP.
* Adjust the gfx12+ calculations so that XeHP will automatically be
  handled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>
 2022-01-11 20:06:02 +00:00
Jordan Justen 0fc93928f1 isl: Don't enable HDC:L1 caches on DG2 
The MOCS entry used for this on Tigerlake doesn't exist on DG2.

Ref: aca31baafc ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14467>
 2022-01-10 21:20:03 +00:00
Nanley Chery 91128b1a0f intel/isl: Require aux map for some 64K alignment 
The comment states that 64K alignment of surfaces is required when an
aux map is present on the platform. However, the code checks for GFX12
instead of dev->info->has_aux_map. Update the code to match the comment.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>
 2021-12-11 04:14:20 +00:00
Dave Airlie d051854cca treewide: drop mtypes/macros includes from main 
These aren't required in lots of places, so remove them.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127>
 2021-12-08 22:14:45 +00:00
Nanley Chery 0733266706 intel/isl: Drop extra devinfo checks for CCS support 
These checks are done in isl_format_supports_ccs_*. Since
isl_surf_supports_ccs calls these functions, it doesn't need to check
them itself.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14082>
 2021-12-07 23:31:23 +00:00
Nanley Chery 0e075227d8 intel/isl: Restore CCS_E support for YUYV and UYVY 
These formats are used when creating surfaces with the
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS modifier.

Makes iris pass the out-of-tree piglit test,
ext_image_dma_buf_import-intel-modifiers.

Fixes: 1433fe7860 ("intel/isl: Unify fmt checks in isl_surf_supports_ccs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14082>
 2021-12-07 23:31:23 +00:00
Kenneth Graunke 2d7c25fb9d isl: Move some genxml surface state helpers into an include file 
On XeHP, the XY_BLOCK_COPY_BLT command has a number of fields that
describe the layout of the surface, much like SURFACE_STATE does.

Several of them are encoded in such a similar manner that we really
would like to reuse the isl helpers for emitting those.  This commit
moves them into a new isl_genX_helpers.h file which I can include
from the BLORP code.  (The alternative would be to add XY_BLOCK_COPY_BLT
filling commands to isl, but that...seems more like a BLORP feature.)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14094>
 2021-12-06 17:23:56 -08:00
Nanley Chery 1433fe7860 intel/isl: Unify fmt checks in isl_surf_supports_ccs 
On TGL+, require that the surface format supports CCS_E in order to
support CCS. This aligns with the ISL code that pads the primary
surface for CCS on this platform.

Pre-TGL, require support for either CCS_D or CCS_E.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12398>
 2021-12-01 20:36:38 +00:00
Nanley Chery caa998ca8f intel/isl: Allow creating non-Y-tiled ASTC surfaces 
The sampler can only decode ASTC surfaces that are Y-tiled. ISL has
been asserting this restriction at surface creation time.

However, some drivers want to create a surface that is only used for
copying compressed data. And during the copy, the surface won't have a
compressed format.

To enable this behavior, we choose to move the tiling assertion to the
moment a surface state is created for the sampler.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13881>
 2021-11-30 13:36:35 +00:00
Jordan Justen 29c2f32a57 intel/dev: Add platform enum with DG2 G10 & G11 
Based on Lionel's "intel/devinfo: store the different kind of DG2".

Ref: 361b3fee3c ("intel: move away from booleans to identify platforms")
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797>
 2021-11-15 21:39:27 +00:00
Lionel Landwerlin 361b3fee3c intel: move away from booleans to identify platforms 
v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
 2021-11-08 16:48:06 +00:00