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136190 Commits

Author SHA1 Message Date
Sagar Ghuge f78e33aa1a intel/compiler: Set correct return format for brw_SAMPLE 
on GFX8 onwards, we have only single bit to determine correct return
format.

v2:
- Define macro and use it instead of hardcoded value. (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
 2021-11-22 21:27:30 -08:00
Emma Anholt 7603187aec nir: Un-inline more of nir_builder.h. 
Cuts another 470KB of libnir.a in my release build.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13889>
 2021-11-22 20:40:47 +00:00
Emma Anholt d9bfcf5f5b nir: Un-inline nir_builder_alu_instr_finish_and_insert() 
This function is big and I don't think it will won't get meaningfully
constant-propagated during inlining without LTO.  Move it to a .c file so
we just have one copy, saving 2.8MB from libnir.a on an amd64 release
build.

      text       data        bss      total filename
before:
  18953406    7768312     687260   27408978 build-release/driver-symlinks/iris_dri.so
   9734366    5542453     481692   15758511 build-release/lib/libvulkan_intel.so
  28687772   13310765    1168952   43167489 (TOTALS)

after:
  15478350    7767864     687260   23933474 build-release/driver-symlinks/iris_dri.so
   6810366    5541685     481692   12833743 build-release/lib/libvulkan_intel.so
  22288716   13309549    1168952   36767217 (TOTALS)

No statistically significant performance difference on iris shader-db, n=8.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13889>
 2021-11-22 20:40:47 +00:00
Ilia Mirkin 3b5b4b5d45 nir: apply interpolated input intrinsics setting when lowering clipdist 
For drivers that use this in fragment shaders, load_input is going to
produce incorrect results (flat-shaded values).

Fixes clipping tests on a4xx.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13900>
 2021-11-22 20:11:19 +00:00
Ilia Mirkin df934873e1 nir: always keep the clip distance array size updated 
Drivers expect to know the number of clip distances irrespective of
whether compact arrays are used or not.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13900>
 2021-11-22 20:11:19 +00:00
Rhys Perry cc2894345f aco/spill: use spills_entry instead of spills_exit to kill linear VGPRs 
If a predecessor has only spilled constants (no temporaries), spills_exit
will be empty.

fossil-db (Sienna Cichlid):
Totals from 2 (0.00% of 128647) affected shaders:
Latency: 139106 -> 139104 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5633
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13821>
 2021-11-22 19:46:22 +00:00
Ilia Mirkin bb6fb6065f freedreno/a[345]xx: fix unorm/snorm blend factors when they're "over" 
The float value may be out of range, so must be clamped to the allowed
range. Unclear if a3xx also has a SNORM factor that we're just missing
there, but that will be a separate investigation.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13903>
 2021-11-22 18:09:44 +00:00
Ilia Mirkin 43f94ee9f1 freedreno/a5xx: add missing L8A8_UNORM format to support TBOs 
Fixes arb_texture_buffer_object-formats test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13906>
 2021-11-22 17:44:59 +00:00
Ilia Mirkin c87967bf17 freedreno/a4xx: add some missing legacy formats to help TBOs 
Unlike with regular textures, we really have to support all the formats
directly for TBOs to work properly. Add the missing formats to fix
arb_texture_buffer_object-formats piglit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13906>
 2021-11-22 17:44:59 +00:00
Ilia Mirkin 5a69f34aeb freedreno/a4xx: add missing SNORM formats to help tests pass 
Otherwise some of these fall back to RGBA_SNORM, which can screw up
blend factors.

Fixes spec@ext_texture_snorm@fbo-blending-formats.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13904>
 2021-11-22 17:18:56 +00:00
Alyssa Rosenzweig c6ca2d1929 panfrost: Handle AFBC_FEATURES in drm-shim 
Fixes the warning with drm-shim:

   Unknown DRM_IOCTL_PANFROST_GET_PARAM 40

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>
 2021-11-22 13:12:20 +00:00
Alyssa Rosenzweig a777e38cf9 panfrost: Collapse 0 parameters in drm-shim 
Makes the code a bit more readable, since this is a sensible default for
many parameters.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13894>
 2021-11-22 13:12:20 +00:00
Iago Toral Quiroga 7fec4f4135 broadcom/compiler: fix scoreboard locking checks 
According to the spec the hardware locks the scoreboard on the first
or last thread switch (selected via shader state) and any TLB accesses
executed before this are not synchronized by hardware.

This change updates the logic to ensure we respect this requirement
and that we don't assume that the lock is acquired automatically
on the first TLB access, which is not valid at least since V3D 4.1+.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>
 2021-11-22 12:53:43 +00:00
Iago Toral Quiroga bd7584c16b broadcom/compiler: don't allow RF writes from signals after thrend 
Writes to physical registers are not allowed after thread end. We
were checking this for ALU writes, but we need to check it for
signal writes too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13910>
 2021-11-22 12:53:43 +00:00
Danylo Piliaiev ed16eedb2d ir3: print half-dst/src for ldib.b/stib.b 
So it would print:
 ldib.b.untyped.1d.u16.1.imm.base0 hr0.z, r0.x, 0
instead of:
 ldib.b.untyped.1d.u16.1.imm.base0 r0.z, r0.x, 0

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13876>
 2021-11-22 12:32:15 +00:00
Lionel Landwerlin 5a2cff9bc8 intel: move timestamp scaling helper to intel/perf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 6126742648 intel/ds: remove verbose messages 
At high frequency sampling, this generates a lot of messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin bd104d5b1a intel/pps: tweak intel config some more 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 3d71e35857 intel/ds: isolate intel/perf from the pps-producer 
Otherwise we need to include intel headers in generic code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin ed9116e545 intel/ds: drop unused constructors 
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 215dbfd131 intel/perf: track end timestamp of queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 4ef6698a26 intel/ds: drop timestamp correlation code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 21a1c6995c pps: fixup sporadic missing counters 
The issue seems to be that without proper timestamps & clock_id, the
recording might discard some packets if they go backward in time.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 120f24cb36 intel/perf: add a helper to read timestamp from reports 
On newer HW it will require more work than just reading a dword. It
could also vary depending on the report format.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Lionel Landwerlin 8657fa6b86 pps: allow drivers to report timestamps in their own time domain 
For this each driver must :

  - report its clock_id (if no particular clock just default to cpu
    boottime one)

  - be able to sample its clock (gpu_timestamp())

The PPSDataSource will then emit timestamp correlation events in the
trace ensuring perfetto is able to display GPU & CPU events
appropriately on its timeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
 2021-11-22 11:52:46 +00:00
Juan A. Suarez Romero 457dbb81f5 broadcom/compiler: apply constant folding on early GS lowering 
This solves a case where a NIR geometry shader was storing the output in
a non-constant:

  vec4 32 ssa_1 = load_const (0xc0800000 /* -4.000000 */, 0xc1100000 /* -9.000000 */, 0x40400000 /* 3.000000 */, 0x40e00000 /* 7.000000 */)
  vec1 32 ssa_7 = load_const (0x00000000 /* 0.000000 */)
  vec1 32 ssa_8 = load_const (0x00000001 /* 0.000000 */)
  vec1 32 ssa_9 = iadd ssa_7, ssa_8
  vec1 32 ssa_19 = mov ssa_1.x
  intrinsic store_output (ssa_19, ssa_9) (1, 1, 0, 160, 288) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=32 slots=2 gs_streams(x=0 y=0 z=0 w=0) */

When lowering the VPM output we check if the destination (ssa_9 in this
case) is a constant to add to the VPM offset. We run a constant folding
optimization in an earlier VS lowering, and we should do the same for
GS.

This fixes multiple dEQP-VK.pipeline.interface_matching.* failures.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>
 2021-11-22 09:32:50 +00:00
Juan A. Suarez Romero 7b21635057 broadcom/compiler: handle array of structs in GS/FS inputs 
While fragment and geometry shader were handling structs as inputs, they
weren't doing for it arrays of structures.

This fixes multiple dEQP-VK.pipeline.interface_matching.* failures and
assertions.

v2:
 - Fix style (Iago).

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13884>
 2021-11-22 09:32:50 +00:00
Lionel Landwerlin c5a42e4010 intel/fs: fix shader call lowering pass 
Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.

v2: rewrite with nir_shader_instructions_pass() (Jason)

v3: handle everything in switch (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 423c47de99 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>
 2021-11-22 08:17:26 +00:00
Alex Xu (Hello71) 8570a2a280 Use initial-exec TLS for glibc only, enable TLS elsewhere 
It is not portable to use initial-exec TLS in dlopened libraries. glibc
and FreeBSD allocate extra memory for extra initial-exec variables
specifically for libGL, but other libcs including musl do not.

Keep initial-exec disabled on FreeBSD since it is apparently broken for
some reason:

https://gitlab.freedesktop.org/mesa/mesa/-/issues/966#note_394512
https://github.com/jbeich/mesa/commit/81dbdb15d55054242eded0eb2f32621d583c1aaf

Enable TLS on OpenBSD and Haiku based on the u_thread.h comment that
emutls is better than pthread_getspecific, which seems plausible given
that emutls has strictly more information to work with.

Fixes #966.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12722>
 2021-11-20 11:56:34 -05:00
Ilia Mirkin df005c2a65 mesa: move around current texture object fetching 
We have to validate the target before fetching the current texture
object. Move this so that it happens later.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
 2021-11-19 20:45:35 -05:00
Ilia Mirkin d814539c2b mesa: check target/format for Tex(ture)StorageMem* 
Noticed while doing an audit around _mesa_get_current_tex usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13767>
 2021-11-19 20:45:13 -05:00
Marek Olšák cdeecadcb6 radeonsi: deduplicate min_esverts code in gfx10_ngg_calculate_subgroup_info 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 9d7ac70ffb radeonsi: implement shader culling in GS 
It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 492a61fe72 radeonsi: don't use ctx.stage outside of si_llvm_translate_nir 
si_llvm_translate_nir() changes ctx.stage, so the outside code shouldn't
use it. This hasn't caused any issues yet. Since ctx.stage starts as 0,
the first use in this commit was a tautology.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 1c5899900d radeonsi: simplify si_get_vs_key_outputs for GS 
ngg_culling is always 0 when GS is enabled. This will change in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák a368385b23 radeonsi: add is_gs parameter into si_vs_needs_prolog 
and disable the VS prolog code for GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák f96d1757bb radeonsi: restructure code that declares merged VS-GS and TES-GS SGPRs 
no change in the SGPR layout

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Marek Olšák 2418da2d4a radeonsi: separate culling code from VS/TES (to be reused by GS) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
 2021-11-20 00:03:45 +00:00
Nicholas Bishop 37c3e16d35 mesa/get: allow NV_pixel_buffer_object constants in GLES2 
The NV_pixel_buffer_object extension can be available in a GLES2
context, so the PIXEL_PACK_BUFFER_BINDING/PIXEL_UNPACK_BUFFER_BINDING
constants should also be available.

Tested on 8086:2e12, "Mesa DRI Intel(R) Q45/Q43 (ELK)".

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5655
Signed-off-by: Nicholas Bishop <nicholasbishop@google.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13862>
 2021-11-19 23:21:52 +00:00
Jesse Natalie b8f41c5c4e d3d12: Validate opened D3D12 resource matches pipe template 
Unlike Linux dma-bufs, D3D12 resources are strongly typed, and
can't necessarily just reinterpret the memory arbitrarily.

Allow importing resources with no description coming from the frontend,
and populate the resource desc from the driver instead. If there was
a template, make sure that it matches the incoming resource.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 9740141b2e d3d12: Generate a pipe format -> typeless mapping table too 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie ca7d4fcb3f d3d12: Generate format table using a macro list 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 25bcc56027 d3d12: Make format list all use macros 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 96012b686e d3d12: Handle import/export of fd shared handles 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 31c7a04b47 winsys/d3d12: Populate winsys handle format 
All other winsys handle users do so, and a future commit will
start caring about it.

Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 2771fd4a3f gallium, windows: Use HANDLE instead of FD for external objects 
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 5bfbf4bec9 microsoft/compiler: Handle GLES external textures 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie 2188607014 d3d12: Support RGBX formats mapped to RGBA 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie ab9948997a d3d12: Support PIPE_CAP_MIXED_COLOR_DEPTH_BITS 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00
Jesse Natalie e0576ec148 d3d12: Support BGRA 555 and 565 formats 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13054>
 2021-11-19 22:54:46 +00:00