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1499 Commits

Author SHA1 Message Date
Simon Ser 92470b3d74 amd/common: introduce ac_surface_print_info 
This is mostly copied from si_print_texture_info, with the si-specific
bits removed. Moving it into common code will allow to use it from both
radeonsi and radv.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>
 2020-11-13 10:30:37 +01:00
Bas Nieuwenhuizen f7a4051b83 radeonsi: Check pitch and offset for validity. 
And lack of overflows, which should help for security.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>
 2020-11-13 03:27:28 +00:00
Bas Nieuwenhuizen 395dac7bf9 amd/common: Add modifier tests. 
This primarily tests that:
 - multiple GPUs with the same GPU modifier parameters result
   in the same tiling layout.
 - The size & alignment calculations don't change for a given
   modifier & image parameters.

It does this primarily based on addrlib. Radeonsi has used addrlib
for the retiling of displayable DCC for a while already, so the
DCC tiling should be pretty reliable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>
 2020-11-13 03:27:28 +00:00
Bas Nieuwenhuizen 0833dd7d12 amd/common: Add support for modifiers. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>
 2020-11-13 03:27:28 +00:00
Rhys Perry 8570de72f5 amd/common: add PIPE_FORMAT_R64_{UINT,SINT} to GFX10 format table 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7234>
 2020-11-09 18:28:59 +00:00
Marek Olšák 3c2489d2e4 amd: print NUM_PKRS with AMD_DEBUG=info on gfx10.3 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7264>
 2020-10-23 20:51:25 -04:00
Marek Olšák 989cc76f0c amd: replace 0x028848 with the register definition 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7264>
 2020-10-23 20:51:22 -04:00
Samuel Pitoiset bf66bbda80 ac: add an option to dump GPU info to a file 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7233>
 2020-10-23 07:35:00 +00:00
James Park af8d488ea5 util,ac,aco,radv: Cross-platform memstream API 
POSIX memstream is not available on Windows.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7143>
 2020-10-19 03:37:42 -07:00
James Park 28d02b9d3e ac,amd/llvm,radv: Initialize structs with {0} 
Necessary to compile with MSVC.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7123>
 2020-10-14 12:15:23 +00:00
Bas Nieuwenhuizen 1fb3e1fb70 radv: Fix mipmap extent adjustment on GFX9+. 
With arrays we really have to use the correct size for the base
mipmap to get the right array pitch. In particular, using
surf_pitch results in pitch that is bigger than the base mipmap
and hence results in wrong pitches computed by the HW.

It seems that on GFX9 this has mostly been hidden by the epitch
provided in the descriptor but this is not something we do on
GFX10 anymore.

Now this has some draw-backs:

1. normalized coordinates don't work
2. Bounds checking uses slightly bigger bounds.

2 mostly is not an issue as we still ensure that they're within
the texture memory and not overlapping other layers/mips, but
we can't properly ignore writes.

1 is kinda dead in the water ... On the other hand I'd argue that
using normalized coords & a filter for sampling a block view of
a compressed format is extraordinarily useless.

The old method we employed already had these drawbacks for everything
except the base miplevel of the imageview.

AFAICT this is the same tradeoff AMDVLK makes and no CTS test hits
this. (once it does I think the HW is dead in the water ... Only
workaround I can think of is shader processing which is hard because
we don't know texture formats at compile time.)

I also removed the extra calculations when the image has only 1 mip
level because they ended up being a no-op in that case.

CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2292
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2266
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2483
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2906
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3607
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7090>
 2020-10-12 21:00:00 +00:00
Samuel Pitoiset b0829c6af7 radv: replace RADV_ALPHA_ADJUST by AC_FETCH_FORMAT 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7065>
 2020-10-12 13:13:40 +00:00
Samuel Pitoiset 5000c344cc ac/llvm: move AC_FETCH_FORMAT to non-LLVM code 
While we are it, give it a name.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7065>
 2020-10-12 13:13:40 +00:00
Marek Olšák a4e4644eff ac/surface: fix valgrind warnings in DCC retile tile lookups 
==12920== Conditional jump or move depends on uninitialised value(s)
==12920==    at 0x8F39391: util_fast_urem32 (fast_urem_by_const.h:71)
==12920==    by 0x8F39391: hash_table_search (hash_table.c:285)
==12920==    by 0x8B06D5D: ac_compute_dcc_retile_tile_indices (ac_surface.c:136)

Fixes: a37aeb128d "amd/common: Cache intra-tile addresses for retile map."

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7055>
 2020-10-09 23:13:40 +00:00
Pierre-Eric Pelloux-Prayer f5ec617677 ac/gpu_info: add detection of TMZ support 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6049>
 2020-09-24 14:51:16 +00:00
Marek Olšák 283686ad67 amd: add VanGogh support 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6820>
 2020-09-22 16:50:07 +00:00
Marek Olšák d7495bd123 amd: add Dimgrey Cavefish support 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6820>
 2020-09-22 16:50:07 +00:00
Bas Nieuwenhuizen ecc19e9819 ac/surface: Fix depth import on GFX6-GFX8. 
Lets just do depth interop imports by convention between radv and
radeonsi for now. The only thing using this should be Vulkan interop
anyway.

CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6617>
 2020-09-20 23:51:58 +00:00
Bas Nieuwenhuizen c6c1fa9a26 radeonsi: Put retile map in separate buffers. 
The retile maps are a software mechanism and hence very suceptible
to change. As such I'd like to avoid making it part of the cross
driver ABI.

Ideally we'd just use the cached tile info + a shader to avoid these
buffers altogether.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6783>
 2020-09-19 03:15:25 -04:00
Bas Nieuwenhuizen be48cf804b amd/common: Store non-displayable DCC pitch. 
For DRM planes with modifiers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6783>
 2020-09-19 03:15:14 -04:00
Pierre-Eric Pelloux-Prayer e5fb9dca2a amd/common: switch to 3-spaces style 
Follow-up of !4319 using the same clang-format config.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5310>
 2020-09-07 10:00:29 +02:00
Tony Wasserka 93c8777ace amd/common: Fix various non-critical integer overflows 
The result of 0xf << 28 is a signed integer and hence overflows into the sign
bit. In practice compilers did the right thing here, since the intent of the
code was unsigned arithmetic anyway.

Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6568>
 2020-09-03 20:20:24 +00:00
Marek Olšák b7a6333ee4 amd/registers: switch to new generated register definitions 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6423>
 2020-09-01 08:45:54 -04:00
Marek Olšák 15bd3f3712 ac/gpu_info: set num_tiles_pipes on gfx10+ too 
Based on PAL.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák b11ebbe2f6 amd: enable displayable DCC for everything newer than Navi1x 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
 2020-07-28 19:47:10 +00:00
Marek Olšák abed921ce7 amd: add support for Navy Flounder 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
 2020-07-28 19:47:10 +00:00
Marek Olšák 037b84df11 amd: rename SIENNA -> SIENNA_CICHLID 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
 2020-07-28 19:47:10 +00:00
Bas Nieuwenhuizen fb5237910b amd: Add detection of timeline semaphore support. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5600>
 2020-07-23 17:36:46 +00:00
Marek Olšák 89d2dac554 radeonsi: enable preemption if the kernel enabled it 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák 95c9048591 radeonsi: add debug code for register shadowing 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák 5a5467ccc8 ac: add tables for CP register shadowing 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák dc3dade475 ac: add helper ac_get_register_name 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Pierre-Eric Pelloux-Prayer 87ecfdfbf0 ac/surface: adapt surf_size when modifying surf_pitch 
Otherwise we might get VM_L2_PROTECTION_FAULT_STATUS errors.

Fixes: 8275dc1ed5 ("ac/surface: fix epitch when modifying surf_pitch")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5841>
 2020-07-20 10:32:44 +00:00
Bas Nieuwenhuizen 862d85a63f amd/addrlib: Clean up unused colorFlags argument 
Cleanup.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5865>
 2020-07-18 00:28:35 +00:00
Bas Nieuwenhuizen a37aeb128d amd/common: Cache intra-tile addresses for retile map. 
However complicated DCC addressing is it is still based on tiles.
If we have the intra-tile offsets + tile dimensions we can expand
that to the full image ourselves.

Behavior around ~1080p on a 2500U:

old:
  30-60 ms on every miss

new:
  5 ms initally (miss in the tile cache)
  <0.5 ms afterwards

The most common case is that the tile cache only contains data for
2 tiles, which for Raven/Renoir/Navi14 will be 4 KiB each, so the
size increase is fairly modest.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5865>
 2020-07-18 00:28:35 +00:00
Marek Olšák 55cf97f56e Revert "ac/surface: require that gfx8 doesn't have DCC in order to be displayable" 
This reverts commit 7406ea37e6.

Fixes: 7406ea37 "ac/surface: require that gfx8 doesn't have DCC in order to be displayable"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3190

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5780>
 2020-07-08 19:16:15 +00:00
Marek Olšák 2866a6f78d ac/gpu_info: fix num_physical_sgprs_per_simd for gfx10 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák c7680625c3 ac,winsys/amdgpu: align IBs the same as the kernel 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 556f4458fe amd: add proper definitions for NOP packets 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Samuel Pitoiset 013d096d15 ac: add ac_choose_spi_color_formats() to common code 
It's similar between RADV and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5436>
 2020-06-15 08:16:07 +02:00
Marek Olšák 0b3e344212 ac/surface: don't free dcc_retile_map on failure 
because the hash table now owns it.

Fixes: bd553f0546 - ac/surface: cache DCC retile maps (v2)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
 2020-06-11 10:01:57 +00:00
Marek Olšák 56f2a77a41 ac/surface: enable DCC for the first level in the mip tail on gfx10 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
 2020-06-11 10:01:57 +00:00
Marek Olšák 7406ea37e6 ac/surface: require that gfx8 doesn't have DCC in order to be displayable 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
 2020-06-11 10:01:57 +00:00
Marek Olšák 374f6d568f ac/surface: don't set is_displayable if displayable DCC is missing 
If flags.display isn't set, then displayable DCC will not be computed, so
is_displayable will always be false.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
 2020-06-11 10:01:57 +00:00
Marek Olšák bd553f0546 ac/surface: cache DCC retile maps (v2) 
This reduces overhead when resizing windows or when allocating
similar image sizes over and over again.

v2: optimize the memory footprint of the cache

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Marek Olšák 4cf674c8f7 ac/surface: add a wrapper structure to hold ADDR_HANDLE 
and more things in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Marek Olšák e6996d6fbd amd/addrlib: remove unused members of ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Marek Olšák a99f4d5382 amd/addrlib: don't recompute DCC info for every ComputeDccAddrFromCoord call 
This decreases the DCC retile map overhead from 23% to 18%.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Marek Olšák a1b9eb62f6 ac/surface: don't recompute the DCC retile map for imported textures 
The retile map is not used in this case, and the retile map computation
takes 39% of CPU time when resizing a window.

This brings it down to 23%.

The dcc_retile_use_uint16 setting has to be derived from DCC sizes.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Pierre-Eric Pelloux-Prayer 8275dc1ed5 ac/surface: fix epitch when modifying surf_pitch 
This is needed otherwise it can cause bad rendering of UYVY files.
The align(..., 256 / surf->bpe) constraint comes from addrlib.

Fixes: 69aadc4933 ("radeonsi: fix surf_pitch for subsampled surface")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5314>
 2020-06-10 09:11:23 +00:00