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Author SHA1 Message Date
Eric Engestrom 03f056ea71 ci: skip slow tests on all non-"full" jobs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31828>
 2024-10-25 08:26:31 +00:00
Eric Engestrom bedb2f8a86 ci: rename "merge-skips" to "slow-skips" as they're about to be used outside of merge piplines 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31828>
 2024-10-25 08:26:31 +00:00
Francisco Jerez e2eba3c7da intel/brw/xe2+: Adjust performance analysis divergence weight due to EU fusion removal. 
This reduces the penalty the heuristic gives to SIMD32 shaders
relative to SIMD16 in presence of discard control flow on Xe2+.  The
penalty was meant to account for the inefficient divergence behavior
of SIMD32 shaders on Gfx12.x platforms, since Gfx12 hardware had EUs
bundled in groups of two, and each pair shared control flow logic so
both EUs could only execute instructions in lockstep, which meant that
SIMD32 shaders had an effective warp size of 64 on Gfx12.x.

This change switches back to more optimistic modelling of discard
divergence.  With it we gain about 6% performance in a Shadow of the
Tomb Raider trace (tested on BMG).

One may wonder if there are still workloads that would suffer
materially from enabling SIMD32 for all pixel shaders on Xe2 instead
of using this heuristic, since Xe2 EUs have twice the GRF space, twice
the FPU throughput and better divergence behavior than Xe, but the
answer seems to be yes unfortunately: E.g. Superposition has some
pixel shaders where SIMD32 has substantially worse scheduling due to
the increased number of false dependencies due to higher register
pressure, and using SIMD32 for them reduces performance significantly.
The heuristic seems to model this correctly so it doesn't look like we
can do without it at least right now on Xe2.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31697>
 2024-10-24 22:06:52 +00:00
Kenneth Graunke 7bed11fbde intel/brw: Allow immediates in the BFE instruction on Gfx12+ 
We weren't allowing immediates in BFE at all.  Gfx12+ supports
immediates in src0 (value) and src2 (width), but not src1 (offset).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31437>
 2024-10-24 21:31:28 +00:00
Aditya Swarup e98759c7f4 anv: Use RCS engine for copying stencil resource for gfx125 
HSD 14021541470 lists a HW bug on blitter engine where the compression pairing bit is
not programmed correctly for stencil resources.

Use RCS Engine to perform copy instead.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31792>
 2024-10-24 20:14:13 +00:00
Eric Engestrom b6bd7522f1 all-drivers/ci: drop duplicate flakes lines 
Done programmatically, not manually, so there shouldn't be any incorrect
removal.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Daniel Schürmann 87cb42f953 treewide: don't lower to LCSSA before calling nir_divergence_analysis() 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c8348139fd nir: change signature of nir_src_is_divergent() 
Now, it takes nir_src * instead of nir_src.
Also move the implementation to nir_divergence_analysis.c.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Jordan Justen a4c5bfd34c intel/dev: Use hwconfig for urb min/max entry values 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen 7b86da0ccd intel/dev: Allow specifying a version when to always use hwconfig 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen a71702d342 intel/dev: Simplify DEVINFO_HWCONFIG_KV by adding should_apply_hwconfig_item() 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen b4df9658f5 intel/dev: Rework DEVINFO_HWCONFIG; add DEVINFO_HWCONFIG_KV macro 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Stéphane Cerveau ac2b7d07e4 anv: check that inline query pool is VK_NULL_HANDLE 
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Stéphane Cerveau aaa5770d4b anv: inline query for vulkan video encode 
Follow up of the work performed in decode to
support inline query.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Tapani Pälli dcb88ea4ab anv/iris: add note about Wa_18039438632 for RT flush after SBA 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31801>
 2024-10-24 04:29:56 +00:00
Paulo Zanoni c0bceaf057 brw: don't emit instruction to add zero in spilling code 
When the spill_offset is zero, don't emit an instruction that adds
zero.

Results on MTL:

- Shaders:
instructions helped:   shaders/blender/581.shader_test FS SIMD8:         6760 -> 6759 (-0.01%) (scheduled: none)
instructions helped:   shaders/blender/1017.shader_test FS SIMD8:        6760 -> 6759 (-0.01%) (scheduled: none)
instructions helped:   shaders/blender/1045.shader_test FS SIMD8:        6474 -> 6473 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/723.shader_test FS SIMD8:         6458 -> 6457 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/1042.shader_test FS SIMD8:        6458 -> 6457 (-0.02%) (scheduled: none)
instructions helped:   shaders/blender/917.shader_test FS SIMD8:         4900 -> 4897 (-0.06%) (scheduled: none)
instructions helped:   shaders/blender/455.shader_test FS SIMD8:         4832 -> 4829 (-0.06%) (scheduled: none)

cycles helped:   shaders/blender/917.shader_test FS SIMD8:         891856 -> 891832 (<.01%) (scheduled: none)
cycles helped:   shaders/blender/455.shader_test FS SIMD8:         894692 -> 894660 (<.01%) (scheduled: none)

total instructions in shared programs: 1596934 -> 1596923 (<.01%)
instructions in affected programs: 42642 -> 42631 (-0.03%)
helped: 7
HURT: 0

- Fossils:

Instrs: 151744378 -> 151741213 (-0.00%)
Cycle count: 16007811131 -> 16007643963 (-0.00%); split: -0.00%, +0.00%

Totals from 1353 (0.21% of 632545) affected shaders:
Instrs: 3925143 -> 3921978 (-0.08%)
Cycle count: 2292838118 -> 2292670950 (-0.01%); split: -0.01%, +0.00%

 RELATIVE IMPROVEMENTS - Instrs                                      Before     After      Delta      Percentage
 mesa/benchmarks/gravity_mark/3e9c48cebaddf012/cs/0                  1947       1941       -6         -0.31%
 mesa/steam-native/red_dead_redemption2/571534e21fb7bd2a/fs.8/0      3431       3421       -10        -0.29%
 mesa/steam-dxvk/batman_arkham_city_goty/d783eacc9ebe324d/fs.8/0     717        715        -2         -0.28%
 mesa/steam-dxvk/batman_arkham_city_goty/14e0878a6a9605c9/fs.8/0     724        722        -2         -0.28%
 mesa/steam-dxvk/batman_arkham_city_goty/d859c2ae858269dc/fs.8/0     744        742        -2         -0.27%
 mesa/steam-dxvk/total_war_warhammer3/18b9d4a3b1961616/vs/0          1539       1535       -4         -0.26%
 mesa/steam-dxvk/total_war_warhammer3/a21827ce57dc0e29/vs/0          1539       1535       -4         -0.26%
(and a bunch of others where the delta is -2, -4 or -6)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31694>
 2024-10-23 20:19:48 +00:00
Lionel Landwerlin 68a372f6ce anv: use UINT32_MAX to be consistent 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin b4ae8cf381 anv: reemit push constants on pipeline changes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12058
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin 7d9449c873 anv: fix missing inline parameter emission 
Should only impact Xe2+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Lionel Landwerlin 3a5b9ee59e anv: fix binding table entry count for compute shaders 
We're not using a binding table entry anymore for num_workgroups.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 02294961ee ("anv: stop using a binding table entry for gl_NumWorkgroups")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31799>
 2024-10-23 18:54:39 +00:00
Sviatoslav Peleshko ebd6738260 intel/elk/chv: Implement WaClearArfDependenciesBeforeEot 
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31746>
 2024-10-23 15:02:27 +00:00
Sviatoslav Peleshko 2a4efe21c5 intel/brw/gfx9: Implement WaClearArfDependenciesBeforeEot 
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11928
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31746>
 2024-10-23 15:02:27 +00:00
Rohan Garg 2a34b492d8 anv: Xe2+ doesn't need the special flush for sparse 
Fixes: 4aa3b2d ('anv: LNL+ doesn't need the special flush for sparse')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31737>
 2024-10-22 20:49:07 +00:00
Tapani Pälli dddd765553 anv: implement VF_STATISTICS emit for Wa_16012775297 
Emit dummy VF_STATISTICS state before each VF state.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31759>
 2024-10-22 20:19:48 +00:00
José Roberto de Souza aa5b2c4165 anv: Set recommended values for gfx20 async compute registers in STATE_COMPUTE_MODE 
This recommended values should improve the performance of async
compute in gfx20, we may want to tweek this for Linux but at least
this values should give us a better baseline than default values.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
José Roberto de Souza 2483f8f7cd intel/genxml: Do small fixes in gfx20 definition of STATE_COMPUTE_MODE 
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
José Roberto de Souza 3efba707bf anv: Set all async compute registers in STATE_COMPUTE_MODE 
Setting the missing registers to specification recommended values that
is also the default value, so it is not expected any changes in
behavior or performance here.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
José Roberto de Souza 86ed5ec78e intel/genxml: Append 'Z Async Throttle settings' to gfx125 definition of STATE_COMPUTE_MODE 
DG2 has the 'Force Non-Coherent' fields but MTL and ARL has
'Z Async Throttle settings', so here adding the missing one.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
 2024-10-22 15:24:32 +00:00
Kenneth Graunke 834b919f6a brw: Optimize 16-bit texture fetches later 
At the point we were calling this, we hadn't necessarily cleaned up
derefs via nir_lower_vars_to_ssa, nor movs/vecs via copy propagation,
so it wasn't necessarily easy for this pass to see the actual usage of
the destination.

Moving this later allows us to detect f2f32(txf(...)) and avoid
converting it to a 16-bit txf (why convert with ALU instructions
when the sampler could do it for us?).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31750>
 2024-10-22 01:15:10 +00:00
Eric Engestrom d117411309 {freedreno,intel}/ci: add missing tracking of merge-skips.txt files 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31739>
 2024-10-21 10:22:57 +00:00
Eric Engestrom ee0d782229 {freedreno,intel}/ci: rename "premerge-skips.txt" to "merge-skips.txt" to accurately reflect what they are 
This also means the infrastructure added by @gallo in 1dc64d0613
("ci: Use merge-skips files during merge pipelines") can be used and all
the manual adding of these files can be dropped, reducing the likeliness
of bugs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31739>
 2024-10-21 10:22:57 +00:00
Caio Oliveira 019770f026 intel/brw: Add SHADER_OPCODE_VOTE_* 
Add opcodes for VOTE_ALL, VOTE_ANY and VOTE_EQUAL.  The first two
are also used for the quad variants.  Move their lowering from
NIR conversion to brw_lower_subgroup_ops.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Caio Oliveira f20df2984d intel/brw: Ensure BROADCAST() value respect register alignment 
If we have a non-register-aligned source, MOV it to a new register
so that the invariant expected when generating SHADER_OPCODE_BROADCAST
is respected.

Added to ensure a later patch won't hit the `src.subnr == 0` assertion
in brw_broadcast() generation code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Caio Oliveira d97381efd8 intel/brw: Add fs_builder::BROADCAST() helper 
Include in the helper which already take care of using exec_all() and
taking the first component of the result.  Both are expected by
SHADER_OPCODE_BROADCAST.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Valentine Burley f3ef27e0b9 ci: Add global ANGLE skips for its waiver 
ANGLE has a waiver for certain XFB tests, but this wasn't properly applied
on Alder Lake and these tests weren't skipped there.

Add a global angle-skips.txt file so that we don't have to keep copy-pasting
these skips.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31721>
 2024-10-18 20:39:33 +00:00
Sergi Blanch Torne a41c4cc1fd WIP: Re-enable Comet Lake 
There is a fresher device type with a CML GPU, with also a bigger number of
boards. Those are more reliable, so also we can remove the manual rules.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26830>
 2024-10-18 16:33:15 +00:00
Daniel Stone a5a5a50ae8 ci/angle: Update ANGLE, reduce build times 
ANGLE currently pulls absolutely loads of stuff that we don't need. Fix
it up so we don't need to do that anymore, so it's much faster to build.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31716>
 2024-10-18 10:40:31 +00:00
Lionel Landwerlin 0317c44872 anv: add VK_EXT_host_image_copy support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:37 +00:00
Lionel Landwerlin 3beb269721 anv: factor out sanitizing mmap offset code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:37 +00:00
Lionel Landwerlin b202f0f422 anv: add a host map of image for host image copy usage 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:37 +00:00
Lionel Landwerlin 6e4d527158 anv: wrap binding address setting 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:37 +00:00
Lionel Landwerlin f33fbb215b anv: disable pat compression for host images 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:37 +00:00
Lionel Landwerlin cb9537a815 anv: drop non host memory types for host-transfer on non-rebar 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:36 +00:00
Lionel Landwerlin 1c7d79374f anv: allow subresource queries on non-linear images 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:36 +00:00
Lionel Landwerlin 70a8e5b8a9 isl/tests: add range_B_tile test 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:36 +00:00
Lionel Landwerlin bcc820950d isl: fix range_B_tile end_tile_B value 
Quoting the documentation :

   "The returned range is a half-open interval where all of the
    addresses within the subimage are < end_tile_B."

This is obviously not true with images smaller than a logical tile.
Currently the code return 1.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24276>
 2024-10-18 07:43:36 +00:00
Paulo Zanoni b88bcacf2b anv/trtt: remove useless VK_RESULT checks 
We jump out of the loops whenever result is not VK_SUCCESS, there is
no need to check for it there. I guess I missed this detail in the
most recent rework for this function.

Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31698>
 2024-10-18 04:10:47 +00:00
Paulo Zanoni da396a49a0 anv/trtt: fix the creation of sparse buffers of size 2^32 on 32bit systems 
When the VkBuffer is of size 2^32 (which matches maxBufferSize), we
have vm_bind->size set to 2^32, which is fine because it fits in an
uint64_t. What is not fine is the 'i' variable being size_t, because
on 32bit systems it will loop forever since it will always be smaller
than 2^32.

Credits to Iván for not only reporting it, but also coming up with the
solution at the same time as I did, then testing it.

Cc: mesa-stable
Reported-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31698>
 2024-10-18 04:10:47 +00:00
Lionel Landwerlin 608d521086 elk: Don't apply discard_if condition opt if it can change results 
Replicates the change from 57344052b6 ("intel/brw: Don't apply
discard_if condition opt if it can change results")

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ba9497e66 ("intel/fs: Improve discard_if code generation")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31604>
 2024-10-18 01:57:58 +00:00
Iván Briano 8423998d69 hasvk: fix non matching image/view format attachment resolve 
Port of 5a7e58a430 ("anv: fix non matching image/view format attachment resolve")
to hasvk.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31696>
 2024-10-17 20:24:37 +00:00