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Author SHA1 Message Date
Lionel Landwerlin f5dc88910f anv: remove pre hasvk split assert 
With softpin we should not always expect a BO in addresses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin ae398284c9 anv: limit push constant dirtyness with generation shaders 
We only use the fragment shader push constants.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 2ea106e758 anv: correctly program 3DSTATE_SF in generation shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin e698040061 anv: remove BTI related flush in generation shaders 
Earlier versions of the generation shaders were using the binding
table. We since switch to A64 messages. So the flush can be removed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 1dcb536acd anv: remove copied code from generation shader 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 63fa6d9f49 anv: fix generated forward jump with more than 67M draws 
The issue here is that for draw indirect count variants, we want to
jump after the last generated draw call to the next location where
commands are. But if we have more than 67M draws (8k * 8k chunks), we
only know the location once we've generated each of the 8k * 8k
chunks.

This change adds a CPU side pointer in the push constant struct so
that we can create a single linked list of chunks to edit and go
through to write the correct jump address after all the generated
space has been allocated.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin c1c680c08b anv: correctly reset generation address on command buffer reset 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 4246a519f3 anv: fix incorrect parameter 
cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush takes a value RANDOM/SEQUENTIAL. Not a boolean.
Fortunately this worked okay because true == RANDOM

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20497>
 2023-03-03 11:30:54 +00:00
Lionel Landwerlin 6ee7a2ecfa anv: pull Wa_14016118574 out of some loop not changing state 
The WA is meant to be here to apply some state that is not propagated
properly inside the HW. But if you have a loop like :

for ( ... ) {
  emit(3DPRIMITIVE, some param);
}

You're not really changing any state, just push more draws into the
pipeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f2645229c2 ("anv: implement Wa_14016118574")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21660>
 2023-03-03 09:34:16 +00:00
Lionel Landwerlin d82e8e01c8 anv: fixup condition for Wa_14016118574 
We don't want the WA to kick-in if it's not point/line topology.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f2645229c2 ("anv: implement Wa_14016118574")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21660>
 2023-03-03 09:34:16 +00:00
Lionel Landwerlin f1e4d5c910 anv: fix scratch buffer reloc in 3DSTATE_HS 
We need to have the scratch buffer added to the pipeline BO tracking
list, so it's added to the batch buffer and finally to the execbuffer
list. Otherwise we pagefault (or read the default scratch page on
i915).

Fixes
dEQP-VK.subgroups.ballot_broadcast.graphics.subgroupbroadcast_u16vec4
on CI (and probably other tests).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2028f1caa3 ("anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21653>
 2023-03-02 17:51:41 +00:00
Lionel Landwerlin c914e70bce anv/hasvk: speed up null image/view descriptor writes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21642>
 2023-03-02 15:03:25 +00:00
Dylan Baker a0fa31bcdd intel/dev: create a helper dependency for libintel_dev 
This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Iván Briano 4887b88d22 anv: use the parameter passed to the macro 
The two points calling this macro pass dyn->rs.provoking_vertex to it,
which is why it works, but it's cleaner to use the parameter instead.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21613>
 2023-03-01 19:07:41 +00:00
Dave Airlie 1f0fdcb619 anv: always pick graphics queue to execute prime blits on. 
This will change when we get transfer queues but this should avoid
video queues being picked by accident.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21204>
 2023-03-01 03:37:36 +00:00
Lionel Landwerlin 672b2f9ad1 anv: remove more Gfx7 code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21599>
 2023-02-28 23:49:27 +00:00
Lionel Landwerlin 3cd72a2840 anv: fixup Wa_16011107343 for Gfx12 only 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 75968398f3 ("anv: emit 3DSTATE_HS for each primitive on gfx12")
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21605>
 2023-02-28 23:03:21 +00:00
Marcin Ślusarz e74a3284f5 anv: halve the push constants space in mesh pipelines 
It's only used by fragment shaders, so halving it matches the size
used in the most optimal primitive pipeline (VS + FS).

This change frees some URB space for mesh and task shaders and as
a result improves vk_meshlet_cadscene performance by up to 2%,
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21559>
 2023-02-28 20:18:01 +00:00
David Heidelberg baea3b328b intel/vulkan: add missing dependency on generated headers 
Adding correct dependencies prevents occasional build flakes with parallel builds.

```
FAILED: src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o
ccache cc -Isrc/intel/vulkan/libanv_common.a.p -Isrc/intel/vulkan -I../src/intel/vulkan -Iinclude -I../include -Isrc -I../src -Isrc/mapi -I../src/mapi -Isrc/mesa -I../src/mesa -I../src/gallium/include -Isrc/intel -I../src/intel -Isrc/compiler -I../src/compiler -Isrc/compiler/nir -I../src/compiler/nir -Isrc/vulkan/util -I../src/vulkan/util -Isrc/vulkan/runtime -I../src/vulkan/runtime -Isrc/vulkan/wsi -I../src/vulkan/wsi -Isrc/intel/genxml -Isrc/intel/vulkan/shaders -Isrc/intel/ds -I/usr/local/include -I/usr/local/include/libdrm -fvisibility=hidden -fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -std=c11 -O2 -g -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS '-DPACKAGE_VERSION="23.1.0-devel"' '-DPACKAGE_BUGREPORT="https://gitlab.freedesktop.org/mesa/mesa/-/issues"' -DHAVE_OPENGL=1 -DHAVE_OPENGL_ES_1=1 -DHAVE_OPENGL_ES_2=1 -DHAVE_SWRAST -DHAVE_VIRGL -DHAVE_RADEONSI -DHAVE_ZINK -DHAVE_CROCUS -DHAVE_IRIS -DHAVE_I915 -DVIDEO_CODEC_VC1DEC=1 -DVIDEO_CODEC_H264DEC=1 -DVIDEO_CODEC_H264ENC=1 -DVIDEO_CODEC_H265DEC=1 -DVIDEO_CODEC_H265ENC=1 -DHAVE_X11_PLATFORM -DHAVE_SURFACELESS_PLATFORM -DHAVE_DRM_PLATFORM -DHAVE_XCB_PLATFORM -DHAVE_ST_VDPAU -DENABLE_ST_OMX_BELLAGIO=0 -DENABLE_ST_OMX_TIZONIA=0 -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING -DGLX_USE_DRM -DALLOW_KCMP -DENABLE_SHADER_CACHE -DHAVE___BUILTIN_BSWAP32 -DHAVE___BUILTIN_BSWAP64 -DHAVE___BUILTIN_CLZ -DHAVE___BUILTIN_CLZLL -DHAVE___BUILTIN_CTZ -DHAVE___BUILTIN_EXPECT -DHAVE___BUILTIN_FFS -DHAVE___BUILTIN_FFSLL -DHAVE___BUILTIN_POPCOUNT -DHAVE___BUILTIN_POPCOUNTLL -DHAVE___BUILTIN_UNREACHABLE -DHAVE___BUILTIN_TYPES_COMPATIBLE_P -DHAVE_FUNC_ATTRIBUTE_CONST -DHAVE_FUNC_ATTRIBUTE_FLATTEN -DHAVE_FUNC_ATTRIBUTE_MALLOC -DHAVE_FUNC_ATTRIBUTE_PURE -DHAVE_FUNC_ATTRIBUTE_UNUSED -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT -DHAVE_FUNC_ATTRIBUTE_WEAK -DHAVE_FUNC_ATTRIBUTE_FORMAT -DHAVE_FUNC_ATTRIBUTE_PACKED -DHAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL -DHAVE_FUNC_ATTRIBUTE_ALIAS -DHAVE_FUNC_ATTRIBUTE_NORETURN -DHAVE_FUNC_ATTRIBUTE_VISIBILITY -DHAVE_UINT128 -DHAVE_REALLOCARRAY -D_GNU_SOURCE -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS -DUSE_X86_64_ASM -DMAJOR_IN_SYSMACROS -DHAS_SCHED_H -DHAS_SCHED_GETAFFINITY -DHAVE_LINUX_FUTEX_H -DHAVE_ENDIAN_H -DHAVE_DLFCN_H -DHAVE_SYS_SHM_H -DHAVE_CET_H -DHAVE_SYS_INOTIFY_H -DHAVE_STRTOF -DHAVE_MKOSTEMP -DHAVE_TIMESPEC_GET -DHAVE_MEMFD_CREATE -DHAVE_RANDOM_R -DHAVE_FLOCK -DHAVE_STRTOK_R -DHAVE_GETRANDOM -DHAVE_GNU_QSORT_R -DHAVE_STRUCT_TIMESPEC -DHAVE_PROGRAM_INVOCATION_NAME -DHAVE_ISSIGNALING -DHAVE_POSIX_MEMALIGN -DHAVE_DIRENT_D_TYPE -DHAVE_STRTOD_L -DHAVE_DLADDR -DHAVE_DL_ITERATE_PHDR -DSUPPORT_INTEL_INTEGRATED_GPUS -DHAVE_ZLIB -DHAVE_COMPRESSION -DHAVE_PTHREAD -DHAVE_PTHREAD_SETAFFINITY -DHAVE_LIBDRM -DLLVM_AVAILABLE '-DMESA_LLVM_VERSION_STRING="13.0.1"' -DLLVM_IS_SHARED=1 -DDRAW_LLVM_AVAILABLE -DUSE_LIBELF -DMESA_EXECMEM -DHAVE_LIBUNWIND -DHAVE_OPENMP -DHAVE_DRI -DHAVE_DRI2 -DHAVE_DRI3 -DHAVE_DRI3_MODIFIERS -DHAVE_DRISW_KMS -DHAVE_PERFETTO -mtls-dialect=gnu2 -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=return-type -Werror=empty-body -Werror=incompatible-pointer-types -Werror=int-conversion -Wimplicit-fallthrough -Wmisleading-indentation -Wno-missing-field-initializers -Wno-format-truncation -Wno-nonnull-compare -fno-math-errno -fno-trapping-math -fno-common -Wno-unused-function -Werror=format -Wformat-security -ffunction-sections -fdata-sections -fPIC -DVK_USE_PLATFORM_XCB_KHR -DVK_USE_PLATFORM_XLIB_KHR -DVK_USE_PLATFORM_DISPLAY_KHR -DVK_USE_PLATFORM_XLIB_XRANDR_EXT -Wno-override-init -DANV_SUPPORT_RT=0 -MD -MQ src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -MF src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o.d -o src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -c ../src/intel/vulkan/anv_generated_indirect_draws.c
../src/intel/vulkan/anv_generated_indirect_draws.c:34:10: fatal error: shaders/generated_draws_spv.h: No such file or directory
   34 | #include "shaders/generated_draws_spv.h"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
```

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21592>
 2023-02-28 17:09:32 +01:00
Tapani Pälli 75968398f3 anv: emit 3DSTATE_HS for each primitive on gfx12 
This is Wa_16011107343, same workaround as commit 880a3efe6c
but for gfx12.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21551>
 2023-02-28 08:07:01 +00:00
Emma Anholt d246948ce3 anv: Skip BTI RT flush if we're doing an op that doesn't use render targets. 
rt_flushes emitted on zink sauer.trace --loop=500 -2.02118% +/- 1.15992% (n=8).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21508>
 2023-02-27 21:44:56 +00:00
Emma Anholt 2bd304bc8f anv: Skip the RT flush when doing depth-only rendering. 
The spec citation says it's just for when the RT write message BTI might
point to a different RT, and if we don't have any color attachments then
we won't have one of those at all.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21508>
 2023-02-27 21:44:56 +00:00
Yonggang Luo 669a68489d meson: Use sse2_arg and sse2_args to replace usage of c and c_sse2_args 
And now c_sse2_arg and c_sse2_args are remvoed

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21375>
 2023-02-27 13:50:11 +00:00
Mike Blumenkrantz 7c8a5f6e37 vulkan/wsi: switch to using an options struct for last param 
this makes adding values easier since the drivers won't need to be updated

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21447>
 2023-02-27 13:21:21 +00:00
Lionel Landwerlin 8441d565ec anv: remove assert typed write support when using NULL surface 
A number of apps hit this assert in debug mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21382>
 2023-02-25 09:20:01 +00:00
Iván Briano b71957635f anv: stop tracking color blend state in the pipeline 
Now that all color blend bits are dynamic, emit_cb_state() is doing
almost nothing and half of that is wrong.

In the case that color write enable is dynamic, at the time the pipeline
state is emitted, it sees all the color attachments as having write
disabled and stores the WriteDisabled bit for each channel.
When all dynamic state is flushed, we have the right values already but
the values recorded into the command buffer get ORed with the ones
stored in the pipeline, and so WriteDisabled tag along when they
shouldn't.

Since all disabled color attachments are handled already when dynamic
state is flushed, there's no point in doing so at pipeline creation
time too. And since the only other thing done by emit_cb_state() is
writing three hardcoded values, they might as well be taken care of in
the same place as everything else.

Fixes CTS from the future:
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_equation_*dynamic*
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_all_*

Fixes: fc3fd7c69e (anv: dynamic color write mask)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
 2023-02-24 22:07:52 +00:00
Iván Briano dd5c6446b4 anv: fix testing for dynamic color blend bits 
Fixes: fc3fd7c69e (anv: dynamic color write mask)
Fixes: 9dc6bed9a1 (anv: dynamic state for logic op enable)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
 2023-02-24 22:07:52 +00:00
Faith Ekstrand 96c832c47e spirv: Always emit deref_buffer_array_length intrinsics 
All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Faith Ekstrand a1c82fa42f anv: Drop our manual SSBO size handling 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Sviatoslav Peleshko 07b57deea2 anv: Move WA MEDIA_VFE_STATE after stalling PIPE_CONTROL 
Fixes: bc612536 ("anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3D")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6172
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21472>
 2023-02-24 10:08:43 +00:00
Sviatoslav Peleshko 4bf38f5652 anv: Handle all fields in VkAccelerationStructureBuildRangeInfoKHR 
Add handling of primitiveOffset and firstVertex.

Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8296
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21342>
 2023-02-24 07:08:05 +00:00
Caio Oliveira 8f3d0141de anv, hasvk: Align workaround address to 32B 
Not necessary but, all things being equal, be consistent with Iris.

Now that intel_debug_write_identifiers() already add the padding,
there's no need to include extra "+ 8" to the offset.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
Tapani Pälli 880a3efe6c anv: implement emission of 3DSTATE_HS for Wa_1306463417 
We need to emit 3DSTATE_HS for each primitive with tessellation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli f8a1100ca1 anv: limit generated draws to pipelines without HS stage 
This is done for gfx11 specific workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli 2028f1caa3 anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state 
Patch packs 3DSTATE_HS state during pipeline creation but it
gets emitted only before 3DPRIMITIVE. We will later need this
to implement a workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Chia-I Wu e97ed4fc89 anv: process utrace payloads on queue submission 
anv_QueuePresentKHR is not called by apps that do not use WSI.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21456>
 2023-02-23 18:06:16 +00:00
Lionel Landwerlin ce68824bdf anv: fix invalid masking of 48bit address 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4d05be49c2 ("anv: implement vkCmdTraceRaysIndirect2KHR")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21486>
 2023-02-23 15:02:45 +00:00
José Roberto de Souza a364f23a6c intel: Make gen12 URB space reservation dependent on compute engine presence 
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
Eric Engestrom fbd644c59d meson: replace vk_wsi_args with dependencies to let meson take care of transitivity 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19497>
 2023-02-23 09:42:46 +00:00
Konstantin Seurer 6242fe3923 anv: Use vk_acceleration_structure 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21047>
 2023-02-22 11:58:57 +00:00
Emma Anholt 4cd7976208 anv: Fix gfx8/9 VB range > 32bits workaround detection. 
Since the dirty range started out as 0..0, you would have 0..VBend as the
new dirty range on the first draw, and if your VB was >32b then you'd
flush every time you used it.  Instead, if there's no existing dirty range
then just set it to our new VB's range.

Perf results with zink+anv on my CFL:

sauerbraten:       +24.8182% +/- 0.602077% (n=5)
portal-2-v2.trace: +4.64289% +/- 0.285285% (n=5)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21370>
 2023-02-18 07:25:47 +00:00
Lionel Landwerlin 3b037ac073 anv: fix vma heap memory leak 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a5f9e59ce3 ("anv: Use vma_heap for descriptor pool host allocation")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21385>
 2023-02-17 21:37:34 +00:00
Lionel Landwerlin 18bf85468c anv: track vram only BOs to print things out on ENOMEM execbuf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21380>
 2023-02-17 13:45:00 +00:00
Lionel Landwerlin 0aa44b107a anv: move debug submit to helper and call it on execbuf failure 
Helps telling when you've run out of local memory.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21380>
 2023-02-17 13:45:00 +00:00
Tapani Pälli d53613dbd7 anv: Wa_14016407139, add required pc when SBA programmed 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21374>
 2023-02-17 12:44:00 +00:00
José Roberto de Souza f331bab884 anv: Move execute_simple_batch() and queue_exec_locked() to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
José Roberto de Souza 0c8d8ae13c anv: Add gem_mmap to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
José Roberto de Souza 32a8250b46 anv: Add gem_close to kmd backend 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21255>
 2023-02-15 23:30:58 +00:00
Constantine Shablya 09501fe5a7 anv,hasvk: flush what UNIFORM_READ flushes on SHADER_READ 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8287
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21310>
 2023-02-15 19:53:41 +00:00
Erik Faye-Lund 29ffc79410 meson: don't pass vk wsi args where they don't belong 
Only code that cares about Vulkan WSI should get the corresponding
arguments passed. Otherwise, the Vulkan headers might end up including
other headers that we don't have the correct dependencies passed for.
So let's give those a dedicated variable, and only pass that where it's
actually needed.

Fixes: b39958a3a1 ("anv,nir: Move the ANV YCbCr lowering pass to common code")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8193
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21185>
 2023-02-15 18:35:14 +00:00